Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
FPGAs and eFPGAs Accelerate ML Inference at the Edge (WP026)

With the rapid proliferation of Internet-of-Things (IoT) and billions of connected devices, there is a paradigm shift taking place where big data is not only being processed in the core data center but also at the network edge. Field Programmable Gate Arrays (FPGAs), sitting at the intersection of performance and flexibility, are a promising solution for deep learning edge inference applications.

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Data Orchestration Supports the Next Advance in AI (WP025)

Artificial intelligence (AI) and machine learning (ML) technologies now power a rapidly expanding range of product and applications from deeply embedded systems to hyperscale data-center deployments. Although there is a huge degree of diversity in the hardware designs supporting these applications, all require hardware acceleration. Data orchestration encompasses the pre- and post-processing operations that ensure the data seen by a machine learning engine arrives at an optimal speed and in the most suitable form for efficient processing.

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An FPGA-Based Solution for a Graph Neural Network Accelerator (WP024)

Thanks to the rise of big data and the rapid increase in computing power, machine learning technology has experienced revolutionary development in recent years. Machine learning tasks such as image classification, speech recognition, and natural language processing, operate on Euclidean data with a certain size, dimension, and an orderly arrangement. However, in many realistic scenarios, data is represented by complex non-Euclidean data such as graphs. In this context, many new graph-based machine learning algorithm, or graph neural networks (GNNs), are constantly emerging in academia and industry.

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The AI Evolution Calls for Adaptable Inferencing Platforms (WP023)

Deep learning's demand for computing power is growing at an incredible rate, accelerating recently from doubling every year to doubling every three months. Increasing the capacity of deep neural network (DNN) models has shown improvements across a wide range of areas ranging from natural language processing to image processing. This growth calls for the adoption of customized architectures that squeeze the greatest amount of performance out of each transistor available.

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FPGAs for Advanced Video Processing Solutions (WP022)

While the performance of an ASIC is typically high enough for broadcast-quality video processing, it supports only the feature set conceived of at design time and is not field upgradable. A CPU is the most flexible and easiest to design; however, clock frequencies have plateaued, and the era of dramatic improvements in performance are over. FPGAs represent a good balance between performance and flexibility for this class of applications.

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Title Description Version Released Date Document File
Speedster7t FPGA Datasheet (DS015)

Achronix’s new 7nm Speedster7t FPGA family is specifically designed to deliver extremely high performance for demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center.

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Speedcore eFPGA Datasheet (DS012)

Achronix Speedcore embedded FPGA (eFPGA) IP includes look-up-table, memory, and DSP blocks. Each of these blocks are designed to be modular to allow customers to define any mix of resources required for their end system.

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Speedster7t 7t1500 Pin Table

The pin tables (in Excel format) for the Speedster7t AC7t1500 in the FBGA2597 package.

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Title Description Version Released Date Document File
Understanding ACE Timing Reports (AN024)

Accurate timing constraints and proper understanding of timing analysis reports are critical to successful FPGA design projects. This application note introduces ACE users to the structure of ACE timing reports generated during an ACE place-and-route run.

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Speedcore User Interface Timing Sign-off Methodology (AN009)

Timing sign-off between the host ASIC and the Speedcore boundary is one of the most crucial steps in ensuring proper integration of a Speedcore instance into a customer's SoC.

1.1 Speedcore_User_Interface_Timing_Sign-off_Methodology_AN009.pdf
Migrating to Achronix FPGA Technology (AN023)

Many users transitioning to Achronix FPGA technology will be familiar with existing FPGA solutions from other vendors. Although Achronix technology and tools are similar to existing FPGA technology and tools, there are some differences. Understanding these differences are needed to achieve the very best performance and quality of results (QoR).

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SoC-Speedcore Interface Tests (AN022)

The input and output paths between the host SoC and a Speedcore instance are an important test component. It is essential to have a structure that ties seamlessly to the SoC's test flow without requiring special functions such as loading a bitstream in the Speedcore instance.

1.0 SoC-Speedcore_Interface_Tests_AN022.pdf
Minimizing Latency in Speedster7t and Speedcore Products (AN019)

In many applications, there is a need to minimize interface latency for ASICs and FPGAs, in particular for the SerDes PMA, to gain a competitive advantage and meet or exceed target specifications.

1.1 Minimizing_Latency_in_Speedster7t_and_Speedcore_Products_AN019.pdf
Title Description Version Released Date Document File
Achronix Tool Suite (PB002)

The Achronix Tool Suite works in conjunction with industry-standard synthesis tools, allowing FPGA designers (for both standalone and embedded) to easily map their designs into Achronix FPGA technology. Achronix provides ACE together with an Achronix-optimized version of Synplify Pro from Synopsys, the industry standard for producing high-performance and cost-effective FPGA designs.

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VectorPath S7t-VG6 Accelerater Card

Developed jointly with BittWare, the VectorPath™ S7t-VG6 accelerator card is designed to reduce time to market when developing high-performance compute and acceleration functions for artificial intelligence (AI), machine learning (ML), networking and data center applications.

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Speedster7t FPGAs Product Brief (PB033)

The Achronix Speedster®7t family is a revolutionary FPGA architecture highly optimized to meet the growing demands of AI/ML and high-bandwidth data acceleration applications. Specifically designed for these high-bandwidth workloads, the Speedster7t FPGA family features a revolutionary new 2D network on chip (NoC) and a high-density array of AI/ML optimized machine learning processors (MLP). Blending FPGA programmability with ASIC routing structures and compute engines, the Speedster7t family creates a new “FPGA+” class of technology.

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Speedcore eFPGA Product Brief (PB028)

Speedcore IP is embedded FPGA (eFPGA) that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements.

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Maximize Hardware Assurance Using Embedded FPGAs (PB035)

Implementing a secure IP solution when developing a custom ASIC involves overcoming many risks along the development, manufacturing and supply chain flow. Hardware assurance continues to become more critical for military and defense applications as worldwide threats increase. By using an eFPGA IP solution to store mission critical IP, supply chain security is greatly simplified compared to the traditional ASIC design flow.

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Title Description Version Released Date Document File
Speedster7t Configuration User Guide (UG094)

At startup, Speedster7t FPGAs require configuration by the end user via a bitstream. This bitstream can be programmed through one of four available interfaces in the FPGA configuration unit (FCU), which is logic that controls the configuration process of the Speedster7t FPGA.

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Speedster7t Power User Guide (UG087)

This document describes the different power supplies that are required for the Speedster7t 7t1500 device and voltage tolerance levels for each of them. Also included are the connection guidelines for each of the power rails and recommendations for the power supply network sharing schemes at the board level.

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ACE Installation and Licensing Guide (UG002)

This guide covers software installation and licensing of ACE software under both Windows and Linux operating software.

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ACE User Guide (UG070)

This guide is a reference manual for the ACE, used for placing, routing, configuring, and debugging Speedcore eFPGAs and Speedster FPGAs. ACE works in conjunction with third-party synthesis and simulation tools to provide a complete design environment for Achronix FPGAs

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Speedster7t Ethernet User Guide (UG097)

Speedster7t devices include high-speed Ethernet interfaces, which can support a wide variety of Ethernet packet protocols and speeds of up to 400 Gbps per channel. These Ethernet interfaces are paired with latest generation SerDes which individually support 100 Gbps data rates. With eight of these SerDes per Ethernet interface, each interface can support 2× 400 Gbps Ethernet IP channels.

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