Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
FPGAs Enable the Next Generation of Communication and Networking Solutions (WP021)

Communications and networking systems that extend from the edges of the 5G network to the switches inside data centers are placing extreme pressure on the ability of silicon to support the computational and data-transfer rates they require. Traditionally programmable logic provided the best mixture of flexibility and speed for these systems, but has been challenged in recent years by the increase in speed. Through the inclusion of an innovative, multilevel network on chip that allows data to be streamed easily around the device without impacting the FPGA fabric, the Speedster7t architecture ensures all device resources are used to their full potential.

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Eight Benefits of Using an FPGA with an On-chip High-Speed Network (WP020)

Since the initial introduction of FPGAs decades ago, each new architecture has continued to employ a bit-wise routing structure. While this approach has been successful, the rise of high-speed communication standards has required ever increasing on-chip bus widths to be able to support these new data rates. Achronix's solution was to create a revolutionary 2D high-speed network on chip (NoC) on top of the traditional segmented FPGA routing structure for its new Speedster7t FPGA family.

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Software-Defined Hardware Provides the Key to High-Performance Data Acceleration (WP019)

Across a wide range of industries, data acceleration is the key to building efficient, smart systems. A number of accelerator technologies have appeared to fill the gap that are based on custom silicon, graphics processors or dynamically reconfigurable hardware, but the key to their success is their ability to integrate into an environment where high throughput, low latency and ease of development are paramount requirements. A board-level platform developed jointly by Achronix and BittWare has been optimized for these applications, providing developers with a rapid path to deployment for high-throughput data acceleration. 

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How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity (WP017)

Intelligent server adapters, or SmartNICs, boost server performance in cloud and private data centers by offloading network processing workloads and tasks from server CPUs. Offloading network processing to a SmartNIC is not a new concept — for example, there are NICs that offload some network-processing functions such as checksum computation and segmentation. However, the rapid explosion in data-center network traffic driven by software-defined networking (SDN), Open vSwitch (OVS), and network functions virtualization (NFV) demands a new class of NIC with even greater offload capabilities: the SmartNIC.

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How to Meet Power Performance and Cost for Autonomous Vehicle Systems using Speedcore eFPGAs (WP015)

In the advanced, fully autonomous, self-driving vehicles of the future, the existence of dozens and even hundreds of distributed CPUs and numerous other processing elements is assured. Peripheral sensor-fusion and other processing tasks can be served by ASICs, SoCs, or traditional FPGAs. But the introduction of embedded FPGA blocks such as Achronix's Speedcore eFPGA IP provides numerous system-design advantages in terms of shorter latency, more security, greater bandwidth, and better reliability that are simply not possible when using CPUs, GPUs, or even standalone FPGAs.

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Title Description Version Released Date Document File
Speedster7t FPGA Datasheet (DS015)

Achronix’s new 7nm Speedster7t FPGA family is specifically designed to deliver extremely high performance for demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center.

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Speedcore Gen3 eFPGA Datasheet (DS003)

Achronix's Speedcore embedded FPGA architecture includes look-up-table, memory, and DSP building blocks that are designed in a modular structure which allows customers to define any quantity of resources required for their end system.

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Speedster7t 7t1500 Pin Table

The pin tables (in Excel format) for the Speedster7t AC7t1500 in the FBGA2597 package.

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Speedcore Gen4 eFPGA Datasheet (DS012)

Achronix's Speedcore Gen4 embedded FPGA (eFPGA) IP includes look-up-table, memory, DSP, and machine learning processor (MLP) building blocks. Each of these blocks are designed to be modular to allow customers to define any mix of resources required for their end system.

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Speedster22i HD1000 FPGA Datasheet (DS005)

Speedster22i HD1000 devices run at a maximum rate of 750 MHz and have an effective density of up to one million LUTs. Based on the Intel 22nm process, Speedster22i HD1000 devices are SRAM based and fully reconfigurable.

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Title Description Version Released Date Document File
Minimizing Latency in Speedster7t and Speedcore Products (AN019)

In many applications, there is a need to minimize interface latency for ASICs and FPGAs, in particular for the SerDes PMA, to gain a competitive advantage and meet or exceed target specifications.

1.1 Minimizing_Latency_in_Speedster7t_and_Speedcore_Products_AN019.pdf
Mentor Catapult HLS to Hardware Walkthrough (AN021)

The goal of this demonstration design is to provide the user with an end-to-end experience of taking a design module written in C through Mentor's Catapult HLS to generate an RTL code which can then be run through synthesis (Synplify Pro) and ACE place and route to generate a bitstream.

0.0 Mentor_Catapult_HLS_to_Hardware_Walkthrough_AN021.pdf
Production Testing of Speedcore eFPGAs (AN017)

The robustness of ATE production testing is critical to the success and quality of Speedcore eFPGAs. The overall objectives in the implementation and delivery are to reach coverage metrics and allow for industrystandard DPM targets to be met at minimal cost.

1.0 Production_Testing_of_Speedcore_eFPGAs_AN017.pdf
Running Achronix Tools on Ubuntu (AN006)

The Achronix tool chain is formally supported for a number of operating systems (OSes) as listed in the ACE User Guide (UG001). For these OSes, Achronix guarantees operation, and each release of the tool is thoroughly tested on each of those platforms.

1.1 Running_Achronix_Tools_on_Ubuntu_AN006.pdf
Using Encrypted Source Files with ACE (AN008)

Designers need a way to protect their source IP, and that is often achieved by way of encrypted RTL. Achronix's tool flow using ACE and SynplifyPro supports the use of encrypted IP to enable protection of all or part of an IP's RTL.

1.0 Using_Encrypted_Source_Files_with_ACE_AN008.pdf
Title Description Version Released Date Document File
Maximize Hardware Assurance Using Embedded FPGAs (PB035)

Implementing a secure IP solution when developing a custom ASIC involves overcoming many risks along the development, manufacturing and supply chain flow. Hardware assurance continues to become more critical for military and defense applications as worldwide threats increase. By using an eFPGA IP solution to store mission critical IP, supply chain security is greatly simplified compared to the traditional ASIC design flow.

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VectorPath S7t-VG6 Accelerater Card

Developed jointly with BittWare, the VectorPath™ S7t-VG6 accelerator card is designed to reduce time to market when developing high-performance compute and acceleration functions for artificial intelligence (AI), machine learning (ML), networking and data center applications.

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Speedcore eFPGA Product Brief (PB028)

Speedcore IP is embedded FPGA (eFPGA) that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements.

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Achronix Company Backgrounder (PB029)

Achronix Semiconductor Corporation is a privately held, fabless semiconductor corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market.

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Speedster7t FPGAs Product Brief (PB033)

The Achronix Speedster®7t family is a revolutionary FPGA architecture highly optimized to meet the growing demands of AI/ML and high-bandwidth data acceleration applications. Specifically designed for these high-bandwidth workloads, the Speedster7t FPGA family features a revolutionary new 2D network on chip (NoC) and a high-density array of AI/ML optimized machine learning processors (MLP). Blending FPGA programmability with ASIC routing structures and compute engines, the Speedster7t family creates a new “FPGA+” class of technology.

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Title Description Version Released Date Document File
ACE Installation and Licensing Guide (UG002)

This guide covers software installation and licensing of ACE software under both Windows and Linux operating software.

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ACE User Guide (UG070)

This guide is a reference manual for the ACE, used for placing, routing, configuring, and debugging Speedcore eFPGAs and Speedster FPGAs. ACE works in conjunction with third-party synthesis and simulation tools to provide a complete design environment for Achronix FPGAs

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Speedcore DFT and Test User Guide (UG067)

Design for test (DFT) is an important consideration for Speedcore eFPGAs from the perspective of both Achronix and the ASIC integrator. The programmable nature of Speedcore eFPGAs deliver the inherent benefit of being able to use the programmable logic fabric to test itself. This guide describes Speedcore eFPGAs from a testability perspective and outlines the general features and methodologies that Achronix uses to achieve the necessary coverage.

1.4 Speedcore_DFT_and_Test_User_Guide_UG067.pdf
Speedster7t Network on Chip User Guide (UG089)

The Speedster7t FPGA family of devices has a network hierarchy that enables extremely high-speed dataflow between the FPGA core and the interfaces around the periphery, as well as between logic within the FPGA itself. This on-chip network hierarchy supports a cross-sectional bidirectional bandwidth of 20 Tbps. It supports a multitude of interface protocols including GDDR6, DDR4/5, 400G Ethernet, and PCI Express Gen5 data streams, while greatly simplifying access to memory and high-speed protocols. Achronix's network on chip (NoC) provides for read/write transactions throughout the device, as well as specialized support for 400G Ethernet streams in selected columns. The features of the NoC described in this user guide generally pertain to the entire Speedster7t family of devices. In order to help users understand specific connections and features of the NoC, this user guide focuses on the NoC as implemented in the AC7t1500 device.

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Speedster7t Pin Connectivity User Guide (UG084)

This user guide lists each of the I/O pin groups available in the Speedster7t 7t1500 device, their functionality and recommended connection guidelines. Refer to the Power User Guide for detailed description on the power/gnd pins

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