Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
Software-Defined Hardware Provides the Key to High-Performance Data Acceleration (WP019)

Across a wide range of industries, data acceleration is the key to building efficient, smart systems. A number of accelerator technologies have appeared to fill the gap that are based on custom silicon, graphics processors or dynamically reconfigurable hardware, but the key to their success is their ability to integrate into an environment where high throughput, low latency and ease of development are paramount requirements. A board-level platform developed jointly by Achronix and BittWare has been optimized for these applications, providing developers with a rapid path to deployment for high-throughput data acceleration.

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Enabling the Next Generation of 5G Platforms (WP029)

Radio access networks (RANs) and associated core network hierarchy, which link end-user equipment to both the central telecom network and the cloud, are essential in building ubiquitous cellular connectivity to expand the number and breadth of use cases that can be supported by the technology. This paper outlines the current status of 5G standards and rollout, summarizes the new use cases 5G RANs need to support and examines the standards evolution to support higher bandwidth and additional use cases. Finally, it also explains how Achronix FPGA technology can be utilized by developers to meet the fundamental challenge facing them.

 1.1 Download
The Achronix Integrated 2D NoC Enables High-Bandwidth Designs (WP028)

Devices aimed at addressing modern algorithm acceleration workloads must be able to efficiently move high-bandwidth data streams between high-speed interfaces and throughout the device. Achronix Speedster®7t FPGAs can process these high-bandwidth data streams via an integrated new and highly innovative two-dimensional network on chip (2D NoC). This white paper discusses two methods of implementing a 2D NoC and presents an example design to show how the Achronix 2D NoC improves performance, reduces area, and reduces design time when compared to a soft 2D NoC implementation.

 1.1 Download
Reduce Speech Transcription Costs by up to 90% with CAI (WP030)

Conversational artificial intelligence (CAI) uses deep learning (DL), a subset of machine learning (ML), to automate speech recognition, natural language processing and text to speech using machines. Achronix and Myrtle.ai are teaming up to deliver an ASR platform consisting of a 200W, x16 PCIe Gen4-based accelerator card and the associated software which together can sustain up to 4000 RTS concurrently, processing up to 1 million five-minute transcriptions per 24-hour period — reducing costs by as much as 90% versus cloud-based APIs.

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Achronix FPGAs Optimize AI in Industry 4.0 and 5.0 (WP027)

Industry has come a long way over in the last three hundred years. Machines were first introduced in the 1700s, mainly water and steam driven, introducing the Industrial Revolution in the late 1700s. Automation and computer technology would enter the picture in the late 1960's, paving the way for the eventual automation, artificial intelligence (AI) and networked solutions of today. Although it might appear that humans are no longer in the picture, Industry 5.0 is bringing us full circle by combining the precision and efficiency of robotic systems, driven largely by AI, with the ingenuity and real-time thought of the human mind — all leading to more optimal manufacturing environments.

 1.0 Download
Title Description Version Released Date Document File
Speedcore eFPGA Datasheet (DS012)

Achronix Speedcore embedded FPGA (eFPGA) IP includes look-up-table, memory, and DSP blocks. Each of these blocks are designed to be modular to allow the definition any mix of resources required for a custom end system.

 2.1 Download
Speedster7t FPGA Datasheet (DS015)

The Achronix 7nm Speedster7t FPGA family is specifically designed to deliver extremely high performance for demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center.

 1.7 Download
Speedster7t 7t1500 Pin Table

The pin tables (in Excel format) for the Speedster7t AC7t1500 in the FBGA2597 package.

 2.0 Download
Title Description Version Released Date Document File
PCIe Enumeration of Speedster7t FPGAs (AN027)

This Application Note provides the steps to attain enumeration from a non-enumerated device with a PCIe interface and from an already enumerated device.

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Migrating to Achronix FPGA Technology (AN023)

Many users transitioning to Achronix FPGA technology are familiar with existing FPGA solutions from other vendors. Although Achronix technology and tools are similar to existing FPGA technology and tools, there are some differences. Understanding these differences is necessary to achieving the very best performance and quality of results (QoR).

 1.1 Download
Coding Guidelines for Speedcore eFPGAs (AN003)

This application note details certain specific design elements that, with certain coding constructs and constraints, can improve timing performance or lower resource utilization.

 2.1 Coding_Guidelines_for_Speedcore_eFPGAs_AN003.pdf
Runtime Programming of Speedster FPGAs (AN025)

This application note demonstrates changing the I/O ring configuration registers of a Speedster FPGA while in user mode.

 1.0 Download
Understanding ACE Timing Reports (AN024)

Accurate timing constraints and proper understanding of timing analysis reports are critical to successful FPGA design projects. This application note introduces ACE users to the structure of ACE timing reports generated during an ACE place-and-route run.

 1.0 Download
Title Description Version Released Date Document File
VectorPath S7t-VG6 Accelerator Card

Developed jointly with BittWare, the VectorPath® S7t-VG6 accelerator card is designed to reduce time to market when developing high-performance compute and acceleration functions for artificial intelligence (AI), machine learning (ML), networking and data center applications.

 2022.08.18 Download
Speedster7t FPGAs Product Brief (PB033)

The Achronix Speedster®7t family is a revolutionary FPGA architecture highly optimized to meet the growing demands of AI/ML and high-bandwidth data acceleration applications. Specifically designed for these high-bandwidth workloads, the Speedster7t FPGA family features a revolutionary new 2D network on chip (NoC) and a high-density array of AI/ML optimized machine learning processors (MLP). Blending FPGA programmability with ASIC routing structures and compute engines, the Speedster7t family creates a new “FPGA+” class of technology.

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Achronix Company Backgrounder (PB029)

Achronix Semiconductor Corporation is a privately held, fabless semiconductor corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market.

 1.6 Download
Achronix Tool Suite (PB002)

The Achronix Tool Suite works in conjunction with industry-standard synthesis tools, allowing FPGA designers (for both standalone and embedded) to easily map their designs into Achronix FPGA technology. Achronix provides ACE together with an Achronix-optimized version of Synplify Pro from Synopsys, the industry standard for producing high-performance and cost-effective FPGA designs.

 5.4 Download
Speedcore eFPGA Product Brief (PB028)

Speedcore IP is embedded FPGA (eFPGA) that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements.

 1.8 Download
Title Description Version Released Date Document File
Speedster7t GDDR6 User Guide (UG091)

The Speedster7t FPGA family provides multiple GDDR6 subsystems enabling full utilization of the high-bandwidth efficiency of these interfaces for critical applications. This guide provides the details for implementing the GDDR6 IP in custom designs.

 2.0 Download
ACE User Guide (UG070)

This guide is a reference manual for the ACE, used for placing, routing, configuring, and debugging Speedcore eFPGAs and Speedster FPGAs. ACE works in conjunction with third-party synthesis and simulation tools to provide a complete design environment for Achronix FPGAs

 9.0 Download
Speedster7t Ethernet User Guide (UG097)

Speedster7t devices include high-speed Ethernet interfaces, which can support a wide variety of Ethernet packet protocols and speeds of up to 400 Gbps per channel. These Ethernet interfaces are paired with latest generation SerDes which individually support 100 Gbps data rates. With eight of these SerDes per Ethernet interface, each interface can support 2× 400 Gbps Ethernet IP channels.

 2.1 Download
Software Development Kit User Guide (UG107)

This Guide introduces the Achronix Software Development Kit and details each of the provided structures and functions.

 1.0 Download
Design Flow User Guide (UG106)

This user guide covers various aspects of the Achronix toolchain design flow.

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