|ANIC Network Shell Overview
Filmed at our SC22 booth, this demo overview dives into Achronix's Ethernet network shell (ANIC) — a full ethernet data path built on top of the Speedster7t FPGA from data receive to data transmit at speeds up to 400G. Director of Product Marketing, Ron Renwick, showcases our Achronix Speedster7t FPGA and its features, flexibility, and secret sauce (2D Network-on-Chip) to enable high performance network data acceleration.
|PCIe Gen5 x16 Running on the VectorPath Accelerator Card
In this demo, Achronix engineers show the VectorPath Accelerator Card successfully linking up to a PCIe Gen5 x16 host and write data to and read data from GDDR6 memory. The VectorPath accelerator card featuring the Speedster7t 7t1500 is one of the first FPGAs that can natively support this interface within its PCIe subsystem.
|Speedster7t 2D NoC vs. Traditional FPGA Routing
This demonstration compares an FPGA design utilizing the Speedster®7t 2D Network on Chip (NoC) for routing signals with the FPGA device, versus using traditional FPGA routing. The 2D NoC provides a 40% reduction in logic resources required with 40% less compile time needed versus using traditional FPGA routing.
|Watch PCIe Gen5 Interface Demo Running on a Speedster7t FPGA
PCIe Gen5 is the most advanced PCIe specification available today, providing data link capable of a 32 GT/s for next-generation systems. Start to design your PCIe Gen5 system today using the Achronix Speedster7t FPGA. This demonstration shows a successful PCIe Gen5 link between a Lecroy PCIe exerciser and a Speedster7t FPGA. The Speedster7t family is one of the first FPGAs available now that natively supports the PCIe Gen5 specification.
|Using Speedster7t PCIe Gen4 x16 to Communicate with an AMD Ryzen PC
In this demonstration, the Achronix VectorPath® accelerator card connects to an AMD Ryzen based PC using PCIe Gen4 x16 interface. The host PC issues commands to have the Speedster7t FPGA on the VectorPath accelerator card write and read to external GDDR6 memory on the board. These data transactions are performed using the Speedster7t FPGA’s 2D network on chip or NoC which eliminates the need to write complex RTL code to design the host PC to GDDR6 memory interface.
|400 GbE Running on a Speedster7t FPGA
400GbE is required for next-generation, high-performance networking applications. In this video, Achronix demonstrates 400GbE connectivity on a Speedster7t FPGA integrated into a VectorPath® PCIe accelerator card. The demonstration shows 400GbE traffic generated within the FPGA and transmitted across the FPGA’s 2D network on chip or NoC to the Ethernet subsystem. The 400GbE traffic is then looped back and checked within the FPGA fabric to compare to the original data stream.
|Speedster7t FPGA DDR4 Memory Interface Running at 3,200 Mbps
See a demonstration of a Speedster7t FPGA reading and writing to DDR4 memory components on the VectorPath® accelerator card. This demonstration shows how to configure the interface using ACE design tools, program the FPGA, train the memory link, then issue 8,000 write and read transactions to verify the data. This design uses the Speedster7t 2D network on chip or NoC to route the data from the FPGA fabric to memory interface without a single line of RTL code for this part of the design.