Speedster®7t FPGAs are optimized for high-bandwidth workloads and eliminate the performance bottlenecks associated with traditional FPGAs.
The Speedster7t FPGA family is optimized for high-bandwidth workloads and eliminates the performance bottlenecks associated with traditional FPGAs. Built on TSMC’s 7nm FinFET process, Speedster7t FPGAs feature a revolutionary new 2D network-on-chip (2D NoC), an array of new machine learning processors (MLPs) optimized for high-bandwidth and artificial intelligence/machine learning (AI/ML) workloads, high-bandwidth GDDR6 interfaces, 400G Ethernet and PCI Express Gen5 ports. The 2D NoC connects all of the interfaces to over 80 access points in the FPGA fabric to deliver ASIC-level performance while retaining the full programmability of FPGAs. Get started today with the VectorPath accelerator card, featuring the Speedster7t FPGA.
2D Network on Chip (2D NoC)
Machine Learning Processors
>20 Tbps bandwidth
Interconnects, I/O, memory, internal functional blocks and FPGA fabric.
Reduce routing congestion vs. traditional FPGAs
Simplify FPGA design
112 Gbps SerDes (up to 64)
Up to eight controllers
Up to 4 Tbps bandwidth
Native support for integer, floating point, bfloat16 and block floating point
The Speedster7t FPGA family provides multiple GDDR6 subsystems enabling full utilization of the high-bandwidth efficiency of these interfaces for critical applications. This guide provides the details for implementing the GDDR6 IP in custom designs.
Software-Defined Hardware Provides the Key to High-Performance Data Acceleration (WP019)
Across a wide range of industries, data acceleration is the key to building efficient, smart systems. A number of accelerator technologies have appeared to fill the gap that are based on custom silicon, graphics processors or dynamically reconfigurable hardware, but the key to their success is their ability to integrate into an environment where high throughput, low latency and ease of development are paramount requirements. A board-level platform developed jointly by Achronix and BittWare has been optimized for these applications, providing developers with a rapid path to deployment for high-throughput data acceleration.
The Achronix 7nm Speedster7t FPGA family is specifically designed to deliver extremely high performance for demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center.
This document describes the different power supplies that are required for the Speedster7t 7t1500 device and voltage tolerance levels for each of them. Also included are the connection guidelines for each of the power rails and recommendations for the power supply network sharing schemes at the board level.
The Achronix Speedster®7t family is a revolutionary FPGA architecture highly optimized to meet the growing demands of AI/ML and high-bandwidth data acceleration applications. Specifically designed for these high-bandwidth workloads, the Speedster7t FPGA family features a revolutionary new 2D network on chip (NoC) and a high-density array of AI/ML optimized machine learning processors (MLP). Blending FPGA programmability with ASIC routing structures and compute engines, the Speedster7t family creates a new “FPGA+” class of technology.
FPGAs Enable the Next Generation of Communication and Networking Solutions (WP021)
Communications and networking systems that extend from the edges of the 5G network to the switches inside data centers are placing extreme pressure on the ability of silicon to support the computational and data-transfer rates they require. Traditionally programmable logic provided the best mixture of flexibility and speed for these systems, but has been challenged in recent years by the increase in speed. Through the inclusion of an innovative, multilevel network on chip that allows data to be streamed easily around the device without impacting the FPGA fabric, the Speedster7t architecture ensures all device resources are used to their full potential.
The Speedster7t FPGA family of devices has a network hierarchy that enables extremely high-speed dataflow between the FPGA core and the interfaces around the periphery, as well as between logic within the FPGA itself. This on-chip network hierarchy supports a cross-sectional bidirectional bandwidth of 20 Tbps. It supports a multitude of interface protocols including GDDR6, DDR4/5, 400G Ethernet, and PCI Express Gen5 data streams, while greatly simplifying access to memory and high-speed protocols. Achronix's network on chip (NoC) provides for read/write transactions throughout the device, as well as specialized support for 400G Ethernet streams in selected columns. The features of the NoC described in this user guide generally pertain to the entire Speedster7t family of devices. In order to help users understand specific connections and features of the NoC, this user guide focuses on the NoC as implemented in the AC7t1500 device.
Eight Benefits of Using an FPGA with an On-chip High-Speed Network (WP020)
Since the initial introduction of FPGAs decades ago, each new architecture has continued to employ a bit-wise routing structure. While this approach has been successful, the rise of high-speed communication standards has required ever increasing on-chip bus widths to be able to support these new data rates. Achronix's solution was to create a revolutionary 2D high-speed network on chip (NoC) on top of the traditional segmented FPGA routing structure for its new Speedster7t FPGA family.
How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity (WP017)
Intelligent server adapters, or SmartNICs, boost server performance in cloud and private data centers by offloading network processing workloads and tasks from server CPUs. Offloading network processing to a SmartNIC is not a new concept — for example, there are NICs that offload some network-processing functions such as checksum computation and segmentation. However, the rapid explosion in data-center network traffic driven by software-defined networking (SDN), Open vSwitch (OVS), and network functions virtualization (NFV) demands a new class of NIC with even greater offload capabilities: the SmartNIC.
Speedster7t Machine Learning Processor User Guide (UG088)
The machine learning processor block (MLP) is an array of up to 32 multipliers, followed by an adder tree, an accumulator, and a rounding/saturation/normalize block.The MLP also includes two memory blocks, a BRAM72k and LRAM2k, that can be used individually or in conjunction with the array of multipliers. The number of multipliers available varies with the bit width of each operand and the total width of input data. When the MLP is used in conjunction with a BRAM72k, the amount of data inputs to the MLP block increases along with the number of multipliers available.
Achronix has completed testing and is now demonstrating the 112 Gbps SerDes that will be used in…
5G Infrastructure 5G cellular network technology is driving connectivity for the next generation of application seamlessly with high security and reliability. 5G continues the paradigm of previous cellular standards… more >
Computational Storage Computational storage solutions enhance traditional storage subsystems with more capabilities to reduce data movement and optimize performance and efficiency. The Speedster7t family of FPGAs allow… more >
Defense and Hardware Assurance Defense applications that require hardware assurance and long lifecycles are and ideal fit for FPGA and eFPGA solutions. FPGA or eFPGA based designs can be customized at development time and… more >
Networking Companies building future networks have the challenge of addressing the ever increasing and diverse data demands at an affordable cost. Two new paradigms that has evolved as a result are:… more >
Test & Measurement Test and Measurement tends to be at the leading edge of innovation as older approaches to test new technologies is not practical for technical and cost reasons. Like testers, FPGAs have often been… more >
In this webinar, you will learn how to maximize design performance using FPGAs with embedded PCIe Gen5 interfaces. You’ll see why, in addition to high-speed connectivity, you need the ability to process incoming high-bandwidth data to accelerate application performance.
Block floating point (BFP) is a hybrid of floating-point and fixed-point arithmetic where a block of data is assigned a common exponent. Learn about the only FPGA with machine learning processors that can deliver native BFP capabilities with higher performance and lower power consumption compared to traditional FPGA DSP blocks.
This novel architecture has hundreds of NoC-access-points located throughout the FPGA core that can access off-chip memories and any of the high-speed PCI Express ports. This family of FPGAs also include specialized modes for the high-speed 400G Ethernet ports.
In addition, you will see how data can be streamed across the FPGA fabric using 512 Gbps NoC channels located throughout the FPGA processing array.
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