5G cellular network technology is driving connectivity for the next generation of application seamlessly with high security and reliability. 5G continues the paradigm of previous cellular standards not only in driving bandwidth, but also extending it to many more devices and usage models. The 5G standard envisions connecting billions of devices, supporting much higher data rates and much lower latencies with seamless transition from existing network infrastructure. Network security, scalability and reliability are imperative requirements to realize the use cases across three presumed 5G infrastructure categories: enhanced mobile broadband, IoT and mission-critical applications.Key trends include:
- Increased bandwidth for Enhanced Mobile Broadband and other applications, specifically driving the instantaneous available bandwidth to 10x of the current network throughput.
- Connectivity to many, many more devices, with the advent of cellular connectivity for the Internet of Things (IoT). Expectations are that there will be 50 billion cellular connected devices by 2020.
- Proliferation of new usage models, exerting new requirements onto mobile devices and the cellular infrastructure that they connect to. Some of the examples are:
- Low bandwidth, low power requirements for connecting multiple battery-powered IoT end-points for connectivity and monitoring encompassed within mMTC
- High reliability, low latency cellular for vehicle-to-vehicle and vehicle-to-infrastructure connectivity (C-V2X) to complement existing V2X solutions
- High reliability, low latency support for new and emerging applications like remote surgery and augmented/virtual-reality
- Low latency (<1ms) to meet human level response time for robotics and tactile internet applications such as drones and gaming, respectively
- Emerging need for Edge Analytics and Mobile Edge Compute. Gravity has shifted from the previous assumption of data moving to centralized compute resource for processing, to a new paradigm of the compute resource moving towards where the data is generated. This is being driven by latency requirements of emerging applications and the sheer volume of data and the desire to optimize scarce networking resources.
The new innovations in Speedster7t devices enable developers to rapidly innovate with new network deployments because the 5G network typologies will require different integration strategies for diverse applications. Similar to the requirements for advanced networking, 5G networks will include high throughput packet processing, traffic management, and data-path security. Speedster7t devices enable high performance packet processing and workload acceleration with a 2D Network on Chip (NOC) and bus routing for efficient data transfers. Furthermore, computationally complex signal processing in radio, baseband and backhaul is well suited to the MLP block which efficiently implements matrix multiplication for real and complex numbers. Finally, a key capability of Speedster7t devices is to take the same design and migrate it to embedded FPGA (or FPGA chiplets), providing cost and power reduction along with design reuse.
|Application Requirements||Speedster7t Value|
|High performance packet processing for fronthaul, backhaul, and transport||
|Power-efficient signal processing for emerging algorithmic requirements, for example machine learning applied to network optimization, beamforming and digital predistortion||
|Need for flexibility to adapt to new interface requirements||Fine-grained programmability for adaption to fronthaul interfaces such as CPRI, OBSAI, Radio over Ethernet (RoE), eCPRI, XRAN/ORAN|
|Cost reduction path and smaller form-factor||
|Radio||Baseband||Fronthaul||Access/Transport Backhaul||Cloud RAN|
|Highest Performance SerDes|
|112G multi-standard SR/MR/LR PHY||Yes||Yes|
|Ultra-short reach (USR), extra-short reach (XSR)||Yes||Yes||Yes||Yes|
|Most Advanced Interface IP|
|Ethernet - lanes running up to 100G each for 100G or 400G communication||Yes (100G)||Yes (100G)||Yes|
|SyncE, IEEE1588, time-sensitive networking (TSN)||Yes||Yes||Yes||Yes||Yes|
|PCIe Gen5 – up to 32 GHz per lane and 512 Gbps/td>||Yes|
|DDR4/5 - up to 3,200 MHz, 3DS stacked memory||Yes||Yes||Yes||Yes||Yes|
|Application-specific interfaces (RoE, eCPRI, CPRI, OBSAI)||Yes||Yes||Yes||Yes|
|Terabit Speed Routing|
|Network on chip||Yes|
|Fully flexibility bit-wise routing||Yes||Yes||Yes||Yes||Yes|
|Machine learning processor (MLP)||Yes||Yes|
|Product and/or Cost Reduction Path|
|Migration to embedded FPGA in ASIC SoC||Yes||Yes||Yes|
|FPGA chiplet integrated in-package||Yes||Yes||Yes||Yes|