Revolutionary New 2D Network-on-Chip

With multiple high-speed PCIe Gen5 and 400G Ethernet ports combined with up to eight GDDR6 SDRAM interfaces, the Speedster®7t FPGA family can move a tremendous amount of data among the various I/O ports and to the FPGAs’ on-chip memory and computational resources. Speedster7t FPGAs employ both bit-wise routing of previous FPGA generations and a new innovative 2 dimensional network on chip (2D NoC) to facilitate the significantly faster data-transfer rates required by high-bandwidth acceleration applications.

Managing the Massive Data Flows of the Future

The Speedster7t 2D NoC is designed to easily support the highest performance interface protocols. For example, the rise of 400 Gbps Ethernet within next-generation data centers requires that the FPGA operate at 724 MHz with a 1024-bit internal bus to handle a single 400 Gbps data stream. This combination of bus width and clock rate is simply not possible for any traditional FPGA to close timing on within the programmable fabric. 400 Gbps is the sort of data rate that the Speedster7t FPGA’s on-chip 2D NoC is designed to handle with ease.

The 2D NoC also enables direct connections between the various Speedster7t interface ports. For example, a host processor can transfer data to any of the GDDR6 or DDR4/5 memory controllers from any of the PCIe Gen5 interfaces using the 2D NoC hierarchy alone, simply by configuring the 2D NoC for the task. The designer does not need to design the connection between the interfaces and none of the FPGA's programmable-logic array is used because the 2D NoC manages everything — the programmable interconnect within the FPGA array is not involved in this data transfer.

Data does inevitably need to reach the programmable logic and the MLPs within the FPGA fabric for processing. To support this data traffic, the 2D NoC distributes data throughout the FPGA fabric using a series of high-speed row and column network conduits, distributing data traffic horizontally and vertically throughout the FPGA fabric. Each row or column in the 2D NoC is implemented as two 256-bit, unidirectional, industry-standard AXI channels operating at a transfer rate of 512 Gbps worth of data traffic in each direction simultaneously for each 2D NoC row or column.


Speedster7t Chip Layout


Enabling 400 Gbps Ethernet

The Speedster7t 2D NoC not only supports a packet-based, master/slave transaction model, it also supports Ethernet data streams. To meet the high-bandwidth requirements of 400G Ethernet without consuming overly large portions of the FPGA programmable-logic array and without creating timing-closure challenges, each Speedster7t Ethernet controller has direct access to multiple 2D NoC columns. This innovative scheme automatically divides the 400G Ethernet data stream into four separate 100G data streams that are easily managed in the programmable fabric, simplifying timing closure.