Videos

Video	Title	Published Date
	Achronix Demonstrates Silicon Validation Device with 112 Gbps SerDes Achronix has completed testing and is now demonstrating the 112 Gbps SerDes that will be used in its next- generation FPGAs devices. Fabricated on TSMC’s 7nm FinFET process technology, these 112 Gbps SerDes blocks provide true multi-standard support for a wide range of digital serial communications standards with data rates ranging from 1 Gbps to 112 Gbps.	03/27/2019
	Achronix Speedcore Gen4 eFPGA IP for AI/ML and Networking Hardware Acceleration Steve Mensor, VP of Marketing at Achronix previews the coming announcement of the next-generation Speedcore architecture.	10/26/2018
	Robert Blake at the CASPA 2018 Annual Conference Robert Blake presenting at the CASPA 2018 Annual Conference. Topic: "Addressing AI/ML Hardware Challenges."	10/24/2018
	Steve Mensor at ArmTechCon 2018 Steve Mensor presents at ArmTechCon 2018. Topic: “Accelerate your Arm-based SoC with Speedcore eFPGA IP”	10/24/2018
	Embedded Computing Design Interview with Steve Mensor at Arm TechCon 2018 Brandon Lewis, Editor-in-Chief of Embedded Computing Design sits down with Achronix VP of Marketing, Steve Mensor, to discuss how to deal the growing volume of data that will require to be processed to drive the next wave of AI applications.	10/19/2018
	eFPGA vs. FPGA Design Methodologies Namit Varma, senior director of Achronix’s India Technology Center, discusses the differences between discrete and embedded FPGAs.	10/05/2018
	How to Time an eFPGA, and What Can Go Wrong Namit Varma, senior director of Achronix’s India Technology Center, explains how to time an eFPGA, what can go wrong, what are the different clocking scenarios, and what impact variation has on the process.	08/02/2018
	Increase Performance, Reduce Die Size with Speedcore eFPGA Custom Blocks Flow Achronix Vice President of Marketing, Steve Mensor, speaking at DAC 2018 in San Francisco.	07/27/2018
	Learning to Share – Embedded FPGA Timing Closure Achronix Systems Architect, Kent Orthner, speaking at DAC 2018 in San Francisco.	07/27/2018
	From 40-500 MHz eFPGA to FPGA Chiplet Solution Design and Reuse interview with Steve Mensor, VP of Marketing, at DAC 2018, San Francisco, CA; June 24-28th.	06/28/2018