| Video | Title | Published Date |
|---|---|---|
Nasdaq Trade Talks: Enabling Technology for Data AccelerationAchronix CEO Robert Blake joins Jill Malandrino on Nasdaq #TradeTalks to discuss enabling technology for data acceleration. |
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What Are The Challenges Facing SmartNIC Designers?In this discussion with Electronic Design's Bill Wong, Achronix Director of SmartNIC Product Planning, Scott Schweitzer addresses design issues for SmartNICs ranging from BMC complexes to the need for programmable logic. |
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Achronix Speedster7t FPGA 400G Lab DemoLive demonstration of Speedster®7t 1500 running 400G Ethernet traffic on the VectorPath® accelerator card. |
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BittWare S7t-VG6 VectorPath PCIe Accelerator CardLearn about the S7t-VG6 VectorPath® PCIe accelerator card from BittWare featuring the Achronix Speedster7t FPGA. |
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Achronix Speedster7t FPGA OverviewOverview of features and capabilities of Speedster7t FPGA from Achronix. 2D NoC, machine learning processors, high-performance I/O and GDDR6 memory interfaces. |
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Achronix Speedcore eFPGA IP OverviewOverview of Achronix Speedcore eFPGA IP which is an FPGA IP core that can be embedded into a custom ASIC or SoC device. |
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The Most Exciting Time in the FPGA IndustrySteve Mensor, VP of Sales and Marketing, discusses why this is the most exciting time in the FPGA industry over the past 30 years. He provides an Achronix business update on Speedster7t FPGAs and Speedcore eFPGA IP and the growing opportunities across a wide range of high-performance applications. |
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Achronix Demonstrates Silicon Validation Device with 112 Gbps SerDesAchronix has completed testing and is now demonstrating the 112 Gbps SerDes that will be used in its next- generation FPGAs devices. Fabricated on TSMC’s 7nm FinFET process technology, these 112 Gbps SerDes blocks provide true multi-standard support for a wide range of digital serial communications standards with data rates ranging from 1 Gbps to 112 Gbps. |
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Achronix Speedcore Gen4 eFPGA IP for AI/ML and Networking Hardware AccelerationSteve Mensor, VP of Marketing at Achronix previews the coming announcement of the next-generation Speedcore architecture. |
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Steve Mensor at ArmTechCon 2018Steve Mensor presents at ArmTechCon 2018. Topic: “Accelerate your Arm-based SoC with Speedcore eFPGA IP” |
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Robert Blake at the CASPA 2018 Annual ConferenceRobert Blake presenting at the CASPA 2018 Annual Conference. Topic: "Addressing AI/ML Hardware Challenges." |
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Embedded Computing Design Interview with Steve Mensor at Arm TechCon 2018Brandon Lewis, Editor-in-Chief of Embedded Computing Design sits down with Achronix VP of Marketing, Steve Mensor, to discuss how to deal the growing volume of data that will require to be processed to drive the next wave of AI applications. |
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eFPGA vs. FPGA Design MethodologiesNamit Varma, senior director of Achronix’s India Technology Center, discusses the differences between discrete and embedded FPGAs. |
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How to Time an eFPGA, and What Can Go WrongNamit Varma, senior director of Achronix’s India Technology Center, explains how to time an eFPGA, what can go wrong, what are the different clocking scenarios, and what impact variation has on the process. |
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Increase Performance, Reduce Die Size with Speedcore eFPGA Custom Blocks FlowAchronix Vice President of Marketing, Steve Mensor, speaking at DAC 2018 in San Francisco. |
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Learning to Share – Embedded FPGA Timing ClosureAchronix Systems Architect, Kent Orthner, speaking at DAC 2018 in San Francisco. |
