Videos

Video Title Published Date

Learning to Share – Embedded FPGA Timing Closure

Achronix Systems Architect, Kent Orthner, speaking at DAC 2018 in San Francisco.

From 40-500 MHz eFPGA to FPGA Chiplet Solution

Design and Reuse interview with Steve Mensor, VP of Marketing, at DAC 2018, San Francisco, CA; June 24-28th.

Embedded FPGA: Enabling 5G Infrastructure

Mike Fitton, Senior Director, Strategic Planning, Achronix discusses the role of eFPGAs in 5G infrastructure at the IP SoC Days 2018, Santa Clara, USA.on April 5th, 2018

The Achronix Validation Platform Demonstration

Achronix Speedcore eFPGA IP opens new opportunities for companies looking to integrate embedded FPGA technology into their ASIC or SOC. Speedcore IP is a high-performance, customizable programmable fabric, allowing customers to define the amount of logic, memory, DSP plus their own custom blocks to fit their application requirements. This video demonstrates a validation platform for this game-changing technology.

How to Program an eFPGA

Kent Orthner, system architect at Achronix, talks with Semiconductor Engineering about how to program an embedded FPGA and what's different for ASIC engineers.

eFPGA Verification: How Embedded FPGAs Compare to a Discrete FPGAs and ASICs.

Chris Pelosi, vice president of hardware engineering at Achronix, talks with Semiconductor Engineering about how to verify an embedded FPGA, and how that compares with verification of discrete FPGAs and ASICs.

eFPGA Test

Achronix's Volkan Oktem talks with Semiconductor Engineering about design for test using embedded FPGAs, including how to plan for coverage and how much it will cost.

EDACafé DAC 2017 Interview with Steve Mensor

Interview with Steve Mensor, VP of Marketing at Achronix at DAC 2017 with EDACafé.

The Basics of eFPGA Acceleration