Webinars

Learn about Achronix technology from our experts.
Webinar Title Published Date
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5G Innovation: 5G OpenRAN Overview and Implications

This webinar focuses on the advances made in 5G technology to date, what is planned for 3GPP Releases 17 and 18, and how Achronix FPGA and eFPGA IP technology can be used to enable these new requirements that will result. This educational event will go through a “deep dive” of the 3GPP 5G architecture, use cases and deployment options to enable successful RAN deployments.

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Enhance IoT and 5G Experience Through FPGA Data Acceleration

This webinar discusses the proliferation of IoT and 5G, the explosion of data and how FPGAs enable data acceleration across many applications furthering the ability of IoT and 5G to support this vast expansion of data worldwide.

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Five Reasons Why a High Performance Reconfigurable SmartNIC Demands a 2D NoC Webinar

This webinar will cover five reasons why an FPGA with a 2D NoC is required for the next generation of SmartNICs including:

  • Increasing bandwidth
  • Network virtualization and emerging standards
  • Security and encryption requirements
  • Redefined NVMe storage requirement
  • Design flexibility
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FPGAs Advance Data Acceleration in the Digital Transformation Age Webinar

Worldwide data is growing at an exponential rate, led by 5G, smart phones, streaming services, and the overall digital transformation of the world. In this Webinar, you will learn:

  • Where and how this data is being generated
  • How data centers are being transformed to adapt to this changing paradigm
  • How FPGAs are leading the charge to accelerate compute, networking and storage freeing up CPUs to perform more lucrative workloads
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Best Practices in Designing Rad-Hard and Trusted SoCs with eFPGA IP Webinar

Designing high-performance SoCs for data acceleration applications that require high levels of security and radiation tolerance is a significant challenge for the defense industry. This webinar will provide a technical discussion on the challenges and best practices involved in designing high-performance eFPGA IP for integration into custom rad-hard SoCs.

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Accelerating to 112 Gbps PAM4 Webinar: A Real-World FPGA Implementation

This webinar hosted by Achronix and Samtec will describe how to design 112G SerDes links with Achronix's Speedster7t FPGA and Samtec interconnect technology.

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Autonomous Vehicles: We’re Already There (Sort Of)

Depending on your perspective, autonomous vehicles have been with us for quite some time, or they’re not even close to being here. The former is true in some cases where trials are being run for both passenger vehicles and for trucks. The latter is more the case when you look at mainstream driving down our crowded city streets.

This webinar will look at the components that are needed, both software and hardware, to close the gap between “almost here” and “they’re everywhere.”

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Maximize Performance Using FPGAs with PCIe Gen5 Interfaces

In this webinar, you will learn how to maximize design performance using FPGAs with embedded PCIe Gen5 interfaces. You’ll see why, in addition to high-speed connectivity, you need the ability to process incoming high-bandwidth data to accelerate application performance. 

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Benefits of FPGAs & eFPGA IP in Futureproofing Compute Acceleration

In the quest to accelerate and optimize today’s computing challenges such as AI inference, our system designs have to be flexible above all else. At the confluence of speed and flexibility are today’s new FPGAs and e-FPGA IP. In this episode of Chalk Talk, Amelia Dalton chats with Mike Fitton from Achronix about how to design systems to be both fast and future-proof using FPGA and e-FPGA technology.

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Maximize Hardware Assurance with eFPGA IP

In this webinar you will learn how to maximize hardware assurance (HwA) for critical IP in the semiconductor manufacturing process using eFPGA technology. Hardware assurance is of critical importance for manufacturing semiconductors in applications with heightened security requirements. See how eFPGAs can help to reduce the risk of critical IP getting compromised during the entire life cycle of the ASIC.