|Introduction to Partial Reconfiguration
This introductory overview of the Achronix Partial Reconfiguration (PR) flow showcases the advantage of the Speedster7t FPGA architecture utilizing the 2D NoC to easily replace, move or scale IP blocks throughout the FPGA fabric without the need to recompile or power down the rest of the FPGA.
Our Director of Product Marketing, Bill Jenkins, walks you through the procedure to create multiple PR bitstreams by creating keep-out zones, compiling the different RTL that resides in those zones to create individual bitstreams, creating a top-level bitstream that incorporates each of the IP blocks in an overall FPGA design, and finally how to dynamically program and swap each of the IP blocks during runtime.
|Getting Started with the VectorPath Accelerator Card - Featuring Speedster7t FPGA
This video shows the out-of-the-box experience and how to get started with a VectorPath® accelerator card featuring the Speedster7t FPGA. The video shows what you need to get the card up and running in standalone mode or connected to a host PC.
|ACE Place and Route Tutorial
This video demonstrates the features and capabilities of Achronix ACE development tools for place and routing of Speedster7t FPGAs.
|Best Practices in FPGA Design with Integrated Network on Chip
This video tutorial shows how to create a design that connects and interfaces with the Achronix Speedster7t FPGA network on chip or NoC. You will learn how the placement of NoC access points impacts latency and traffic congestion.
|Introduction to Achronix FPGA Design Tool Flow
Introduction to SynplifyPro and ACE, using the Achronix quick-start design as a demo.
|Introduction to the Speedster7t FPGA Network-on-Chip
Overview of the Achronix network-on-chip (NoC). Describes features, performance, and example transactions.
|Introduction to the Achronix I/O Designer Toolkit
Overview of the Achronix I/O Designer Toolkit. Shows demo of how to configure clocks and other GPIO, PLLs, GDDR6 interfaces, Ethernet, DDR4, PCIe, and the NoC. Highlights features such as changing locations of I/O via drag-and-drop, cloning/copying interfaces for easy reuse in the same or new designs, plus viewing floorplan layout, ball layout and pin locations, and resource utilization.
|Introduction to the Machine Learning Processor
Introduction to the basic architecture of the machine learning processor (MLP) and explains the overall device capabilities. This video covers input data selection, supported number formats, multiplier arrangement, output addition, accumulation and formatting. In addition, this video presents the integer and floating-point libraries of pre-configured components based on the MLP that can be used in many design scenarios.
A collection of training videos covering a range of technical topics.