The Rise of the SmartNIC

Explore Achronix's SmartNIC architecture for 100GbE and beyond

The expansion of data is forcing us to reimagine our data centers at the hardware and systems levels

Almost all of our information is now being digitized, forcing us to reimagine how data centers are built, down to the hardware and systems levels. An emerging data center trend is the rise of the SmartNIC: a programmable accelerator that accelerates and offloads an increasing number of tasks from the server CPU.

To achieve the best balance of performance, efficiency, and cost, SmartNICs require powerful, programmable, and flexible hardware. This is where FPGAs come in. To ensure that the SmartNICs of the future can handle data in a way that is efficient, low latency, and secure, FPGAs are going to be a critical component. Watch this webinar, “The Rise of the SmartNIC”, to learn how Achronix’s FPGAs are poised to enable the SmartNICs of the future.

In this webinar, Scott Schweitzer, Achronix Director of SmartNIC Product Planning and Jon Sreekanth, CTO of Accolade discussed:

  • SmartNIC architecture for 100GbE and beyond
  • Why the Data Plane needs to be dynamically programmable
  • The distinction between packet and flow functions
  • Why simply adding a sea of Arm cores in the Data Plane will not scale
  • The need for a highly performant on-chip network
  • Plus more Q&A from the live audience

What you’ll learn:

  • SmartNIC Architecture
  • How FPGAs Enable SmartNICs
  • Dynamic Programmability of the Data Plane


 

Register to View Webimar

About the Speaker(s)
Scott Schweitzer

Scott Schweitzer – Director, SmartNIC Product Planning

Scott has been a lifelong technology evangelist since his baptism on the altar of the TRS-80. He's written profitable software products for Apple's App Store, built hardware, and formally managed programs at IBM, NEC, Myricom, Solarflar, Xilinx, and Achronix. In 2005, Scott shifted his focus to clustering for HPC and extreme performance networking. As 10GbE adoption ramped up, in 2009, he launched his wildly popular 10GbE.net blog, which eventually became the TechnologyEvangelist.co. This blog now sees thousands of monthly page views, and the accompanying podcast has grown in success. As a Director of SmartNIC Product Management, Scott is focused on networking acceleration. He works with customers and partners to recognize opportunities and define new and innovative solutions.
Jon Sreekanth

Jon Sreekanth – CTO, Accolade Technology

Jon is the Chief Technology Officer at Accolade Technology. Accolade has deep expertise in cybersecurity ethernet packet processing in Xilinx and Achronix FPGAs, with special emphasis on DRAM table-based processing blocks such as flow table, Access Control List (ACL) filtering, deduplication and string search. Accolade has mature shipping n x 100G Smart NIC products and a licensable Verilog codebase and SDK. Jon has over 30 years of ASIC and FPGA design experience, an MSEE from the University of California at Santa Barbara and a BS (BTech) from IIT Madras.