Speedster7t 2D NoC vs. Traditional FPGA Routing

This demonstration compares an FPGA design utilizing the Speedster®7t 2D Network on Chip (NoC) for routing signals with the FPGA device, versus using traditional FPGA routing. The 2D NoC provides a 40% reduction in logic resources required with 40% less compile time needed versus using traditional FPGA routing.

Video Published Date