Speedster7t FPGA DDR4 Memory Interface Running at 3,200 Mbps

See a demonstration of a Speedster7t FPGA reading and writing to DDR4 memory components on the VectorPath™ accelerator card. This demonstration shows how to configure the interface using ACE design tools, program the FPGA, train the memory link, then issue 8,000 write and read transactions to verify the data. This design uses the Speedster7t 2D network on chip or NoC to route the data from the FPGA fabric to memory interface without a single line of RTL code for this part of the design. 

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