Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
Eight Benefits of Using an FPGA with an On-chip High-Speed Network (WP020)

Since the initial introduction of FPGAs decades ago, each new architecture has continued to employ a bit-wise routing structure. While this approach has been successful, the rise of high-speed communication standards has required ever increasing on-chip bus widths to be able to support these new data rates. Achronix's solution was to create a revolutionary 2D high-speed network on chip (NoC) on top of the traditional segmented FPGA routing structure for its new Speedster7t FPGA family.

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Software-Defined Hardware Provides the Key to High-Performance Data Acceleration (WP019)

Across a wide range of industries, data acceleration is the key to building efficient, smart systems. A number of accelerator technologies have appeared to fill the gap that are based on custom silicon, graphics processors or dynamically reconfigurable hardware, but the key to their success is their ability to integrate into an environment where high throughput, low latency and ease of development are paramount requirements. A board-level platform developed jointly by Achronix and BittWare has been optimized for these applications, providing developers with a rapid path to deployment for high-throughput data acceleration. 

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How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity (WP017)

Intelligent server adapters, or SmartNICs, boost server performance in cloud and private data centers by offloading network processing workloads and tasks from server CPUs. Offloading network processing to a SmartNIC is not a new concept — for example, there are NICs that offload some network-processing functions such as checksum computation and segmentation. However, the rapid explosion in data-center network traffic driven by software-defined networking (SDN), Open vSwitch (OVS), and network functions virtualization (NFV) demands a new class of NIC with even greater offload capabilities: the SmartNIC.

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Chiplets – Taking SoC Design Where no Monolithic IC has Gone Before (WP016)

The chiplet movement is a reaction to the rapidly changing IC landscape and the current IC fabrication realities. Engineers are increasingly realizing that it makes little sense to integrate every IP block in a system on one piece of silicon if the fit is poor. There are many advantages with monolithic silicon integration, but those advantages are rapidly being outweighed by the economics of building advanced technology ICs. It is extremely expensive and time consuming to integrate, validate, and tapeout chips that can only be justified with high volume demand. More importantly, adding functionality or creating variations to support multiple end products increases die size and costs. Chiplets are becoming an alternative solution. Fortunately, the ecosystem for chiplets is quickly developing to provide companies a new tool to create highly optimized and cost effective solutions for their various end markets

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Mine Cryptocurrencies Sooner, Faster, and Cheaper with Achronix Speedcore Embedded FPGAs (WP014)

New cryptocurrencies such as Monero introduce ASIC-resistance and memory-hardness to prevent ASICs from being built that give some operators a competitive mining advantage over others who do not have access to the same technology. This white paper discusses the relevant background and presents a solution based on Achronix Speedcore™ embedded FPGAs (eFPGAs), enabling users to regain a highly profitable advantage over competing solutions.

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Title Description Version Released Date Document File
Speedster7t FPGA Datasheet (DS015)

Achronix’s new 7nm Speedster®7t FPGA family is specifically designed to deliver extremely high performance for demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center.

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Speedcore Gen3 eFPGA Datasheet (DS003)

Achronix's Speedcore embedded FPGA architecture includes look-up-table, memory, and DSP building blocks that are designed in a modular structure which allows customers to define any quantity of resources required for their end system.

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Speedster7t 7t1500 Pin Table

The pin tables (in Excel format) for the Speedster7t AC7t1500 in the FBGA2597 package.

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Speedcore Gen4 eFPGA Datasheet (DS012)

Achronix's Speedcore Gen4 embedded FPGA (eFPGA) IP includes look-up-table, memory, DSP, and machine learning processor (MLP) building blocks. Each of these blocks are designed to be modular to allow customers to define any mix of resources required for their end system.

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Speedcore eFPGA Datasheet (DS003)

Achronix's Speedcore embedded FPGA architecture includes look-up-table, memory, and DSP building blocks that are designed in a modular structure which allows customers to define any quantity of resources required for their end system.

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Title Description Version Released Date Document File
Device Binning Methodologies

The manufacturing process for any silicon device inevitably has variations, whether those are in the thickness of a substrate or track, the purity of a conductor, position of the die on the wafer, or one of a myriad of many other physical effects.

1.00 Device_Binning_Methodologies_AN005.pdf
Minimizing Latency in Speedster7t and Speedcore Products

In many applications, there is a need to minimize interface latency for ASICs and FPGAs, in particular for the SerDes PMA, to gain a competitive advantage and meet or exceed target specifications.

1.10 Minimizing_Latency_in_Speedster7t_and_Speedcore_Products_AN019.pdf
Mentor Catapult HLS to Hardware Walkthrough

The goal of this demonstration design is to provide the user with an end-to-end experience of taking a design module written in C through Mentor's Catapult HLS to generate an RTL code which can then be run through synthesis (Synplify Pro) and ACE place and route to generate a bitstream.

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Speedchip Introduction

Next-generation SoC platforms are evolving rapidly to process and move enormous amounts of data from the edge; over the network and to the cloud for high data and compute intensive applications such as AI and machine learning, high-performance computing (HPC) and autonomous driving.

1.00 Speedchip_Introduction_AN020.pdf
Production Testing of Speedcore eFPGAs

The robustness of ATE production testing is critical to the success and quality of Speedcore eFPGAs. The overall objectives in the implementation and delivery are to reach coverage metrics and allow for industrystandard DPM targets to be met at minimal cost.

1.00 Production_Testing_of_Speedcore_eFPGAs_AN017.pdf
Title Description Version Released Date Document File
Maximize Hardware Assurance Using Embedded FPGAs (PB035)

Implementing a secure IP solution when developing a custom ASIC involves overcoming many risks along the development, manufacturing and supply chain flow. Hardware assurance continues to become more critical for military and defense applications as worldwide threats increase. By using an eFPGA IP solution to store mission critical IP, supply chain security is greatly simplified compared to the traditional ASIC design flow.

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VectorPath S7t-VG6 Accelerater Card

Developed jointly with BittWare, the VectorPath™ S7t-VG6 accelerator card is designed to reduce time to market when developing high-performance compute and acceleration functions for artificial intelligence (AI), machine learning (ML), networking and data center applications.

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Achronix Company Backgrounder (PB029)

Achronix Semiconductor Corporation is a privately held, fabless semiconductor corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market.

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Speedster7t FPGAs Product Brief (PB033)

The Achronix Speedster®7t family is a revolutionary FPGA architecture highly optimized to meet the growing demands of AI/ML and high-bandwidth data acceleration applications. Specifically designed for these high-bandwidth workloads, the Speedster7t FPGA family features a revolutionary new 2D network on chip (NoC) and a high-density array of AI/ML optimized machine learning processors (MLP). Blending FPGA programmability with ASIC routing structures and compute engines, the Speedster7t family creates a new “FPGA+” class of technology.

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Speedchip FPGA Chiplets (PB032)

Speedchip FPGA chiplets are optimized for embedding in advanced system-in-package (SiP) solutions such as 2.5D via silicon interposer or organic substrate. With Speedchip chiplets, customers define the functionality for their FPGA chiplet by specifying the number of LUTs, memory blocks, DSP blocks and I/O interfaces needed for their application. Achronix then develops the Speedchip chiplet tailored to the customer’s specification.

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Title Description Version Released Date Document File
ACE Installation & Licensing Guide (UG002)

This guide covers software installation and licensing of ACE software under both Windows and Linux operating software.

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Simulation User Guide (UG072)

The Achronix tool suite includes synthesis and place-and-route software that maps RTL designs (VHDL or Verilog) into Achronix devices. In addition to synthesis and place-and-route functions, the Achronix software tools flow also supports simulation at several flow steps (RTL, Synthesized Netlist, and Post Place-And-Routed Netlist). This guide covers the simulation flow for Achronix devices.

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Speedster7t DDR User Guide (UG096)

The Achronix Speedster7t FPGA family provides DDR subsystems that enable the user to fully utilize the low latency and high-bandwidth efficiency of these interfaces for critical applications such as high-performance compute and machine learning systems. The DDR subsystem supports memory devices and features compliant with JEDEC Standard JESD79-4B.

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ACE User Guide (UG070)

This guide is a reference manual for the Achronix CAD Environment (ACE), used for placing, routing, configuring, and debugging Speedcore eFPGAs and Speedster FPGAs. ACE works in conjunction with third-party synthesis and simulation tools to provide a complete design environment for Achronix FPGAs.

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Speedster7t GDDR6 User Guide (UG091)

The Speedster7t FPGA device family provides multiple GDDR6 subsystems that enables the user to fully utilize the high-bandwidth efficiency of these interfaces for critical applications such as high-performance compute and machine learning systems.The number of GDDR6 subsystems varies with Speedster7t device. For example, the Speedster7t1500 device provides eight GDDR6 interfaces (GDDR6 subsystems), four on the east side and four on the west side of the FPGA. Each subsystem comprises the GDDR6 controller and PHY hard cores and supports up to 512 Gbps; as a result, the 7t1500 offers up to 4 Tbps of total bandwidth. The GDDR6 controller and PHY in the subsystem are implemented as hard IP blocks in the I/O ring of a Speedster7t FPGA. For resource counts for other Speedster7t family members, refer to the  (DS015).

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