Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
FPGAs Enable the Next Generation of Communication and Networking Solutions (WP021)

Communications and networking systems that extend from the edges of the 5G network to the switches inside data centers are placing extreme pressure on the ability of silicon to support the computational and data-transfer rates they require. Traditionally programmable logic provided the best mixture of flexibility and speed for these systems, but has been challenged in recent years by the increase in speed. Through the inclusion of an innovative, multilevel network on chip that allows data to be streamed easily around the device without impacting the FPGA fabric, the Speedster7t architecture ensures all device resources are used to their full potential.

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Eight Benefits of Using an FPGA with an On-chip High-Speed Network (WP020)

Since the initial introduction of FPGAs decades ago, each new architecture has continued to employ a bit-wise routing structure. While this approach has been successful, the rise of high-speed communication standards has required ever increasing on-chip bus widths to be able to support these new data rates. Achronix's solution was to create a revolutionary 2D high-speed network on chip (NoC) on top of the traditional segmented FPGA routing structure for its new Speedster7t FPGA family.

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Software-Defined Hardware Provides the Key to High-Performance Data Acceleration (WP019)

Across a wide range of industries, data acceleration is the key to building efficient, smart systems. A number of accelerator technologies have appeared to fill the gap that are based on custom silicon, graphics processors or dynamically reconfigurable hardware, but the key to their success is their ability to integrate into an environment where high throughput, low latency and ease of development are paramount requirements. A board-level platform developed jointly by Achronix and BittWare has been optimized for these applications, providing developers with a rapid path to deployment for high-throughput data acceleration. 

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How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity (WP017)

Intelligent server adapters, or SmartNICs, boost server performance in cloud and private data centers by offloading network processing workloads and tasks from server CPUs. Offloading network processing to a SmartNIC is not a new concept — for example, there are NICs that offload some network-processing functions such as checksum computation and segmentation. However, the rapid explosion in data-center network traffic driven by software-defined networking (SDN), Open vSwitch (OVS), and network functions virtualization (NFV) demands a new class of NIC with even greater offload capabilities: the SmartNIC.

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Chiplets - Taking SoC Design Where no Monolithic IC has Gone Before (WP016)

The well-documented slowing of Moore's Law is the key driver behind the movement towards the use of chiplets in the design and manufacture of new, high-performance semiconductor devices. While the monolithic IC has been the ultimate design target for many decades, there have always been reasons to build certain devices with multiple die using multi-chip modules (MCMs), whether it was for additional memory capacity or to fabricate chips based on IP blocks that require incompatible IC processes.

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Title Description Version Released Date Document File
Speedcore eFPGA Datasheet (DS012)

Achronix Speedcore embedded FPGA (eFPGA) IP includes look-up-table, memory, and DSP blocks. Each of these blocks are designed to be modular to allow customers to define any mix of resources required for their end system.

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Speedster7t FPGA Datasheet (DS015)

Achronix’s new 7nm Speedster7t FPGA family is specifically designed to deliver extremely high performance for demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center.

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Speedster7t 7t1500 Pin Table

The pin tables (in Excel format) for the Speedster7t AC7t1500 in the FBGA2597 package.

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Title Description Version Released Date Document File
SoC-Speedcore Interface Tests (AN022)

The input and output paths between the host SoC and a Speedcore instance are an important test component. It is essential to have a structure that ties seamlessly to the SoC's test flow without requiring special functions such as loading a bitstream in the Speedcore instance.

1.0 SoC-Speedcore_Interface_Tests_AN022.pdf
Minimizing Latency in Speedster7t and Speedcore Products (AN019)

In many applications, there is a need to minimize interface latency for ASICs and FPGAs, in particular for the SerDes PMA, to gain a competitive advantage and meet or exceed target specifications.

1.1 Minimizing_Latency_in_Speedster7t_and_Speedcore_Products_AN019.pdf
Mentor Catapult HLS to Hardware Walkthrough (AN021)

The goal of this demonstration design is to provide the user with an end-to-end experience of taking a design module written in C through Mentor's Catapult HLS to generate an RTL code which can then be run through synthesis (Synplify Pro) and ACE place and route to generate a bitstream.

0.0 Mentor_Catapult_HLS_to_Hardware_Walkthrough_AN021.pdf
Production Testing of Speedcore eFPGAs (AN017)

The robustness of ATE production testing is critical to the success and quality of Speedcore eFPGAs. The overall objectives in the implementation and delivery are to reach coverage metrics and allow for industrystandard DPM targets to be met at minimal cost.

1.0 Production_Testing_of_Speedcore_eFPGAs_AN017.pdf
Running Achronix Tools on Ubuntu (AN006)

The Achronix tool chain is formally supported for a number of operating systems (OSes) as listed in the ACE User Guide (UG001). For these OSes, Achronix guarantees operation, and each release of the tool is thoroughly tested on each of those platforms.

1.1 Running_Achronix_Tools_on_Ubuntu_AN006.pdf
Title Description Version Released Date Document File
Speedcore eFPGA Product Brief (PB028)

Speedcore IP is embedded FPGA (eFPGA) that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements.

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Maximize Hardware Assurance Using Embedded FPGAs (PB035)

Implementing a secure IP solution when developing a custom ASIC involves overcoming many risks along the development, manufacturing and supply chain flow. Hardware assurance continues to become more critical for military and defense applications as worldwide threats increase. By using an eFPGA IP solution to store mission critical IP, supply chain security is greatly simplified compared to the traditional ASIC design flow.

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VectorPath S7t-VG6 Accelerater Card

Developed jointly with BittWare, the VectorPath™ S7t-VG6 accelerator card is designed to reduce time to market when developing high-performance compute and acceleration functions for artificial intelligence (AI), machine learning (ML), networking and data center applications.

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Achronix Company Backgrounder (PB029)

Achronix Semiconductor Corporation is a privately held, fabless semiconductor corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market.

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Speedster7t FPGAs Product Brief (PB033)

The Achronix Speedster®7t family is a revolutionary FPGA architecture highly optimized to meet the growing demands of AI/ML and high-bandwidth data acceleration applications. Specifically designed for these high-bandwidth workloads, the Speedster7t FPGA family features a revolutionary new 2D network on chip (NoC) and a high-density array of AI/ML optimized machine learning processors (MLP). Blending FPGA programmability with ASIC routing structures and compute engines, the Speedster7t family creates a new “FPGA+” class of technology.

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Title Description Version Released Date Document File
Speedster7t Ethernet User Guide (UG097)

Speedster7t devices include high-speed Ethernet interfaces, which can support a wide variety of Ethernet packet protocols and speeds of up to 400 Gbps per channel. These Ethernet interfaces are paired with latest generation SerDes which individually support 100 Gbps data rates. With eight of these SerDes per Ethernet interface, each interface can support 2× 400 Gbps Ethernet IP channels.

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Speedster7t Power User Guide (UG087)

This document describes the different power supplies that are required for the Speedster7t 7t1500 device and voltage tolerance levels for each of them. Also included are the connection guidelines for each of the power rails and recommendations for the power supply network sharing schemes at the board level.

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Speedster7t IP Component Library User Guide (UG086)

The Achronix Speedster7t macro cell library provides the user with building blocks that may be instantiated into the user’s design. These macros provide access to low-level fabric primitives, complex I/O block, and higher level design components. Each library element entry describes the operation of the macro as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design.

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ACE Installation and Licensing Guide (UG002)

This guide covers software installation and licensing of ACE software under both Windows and Linux operating software.

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ACE User Guide (UG070)

This guide is a reference manual for the ACE, used for placing, routing, configuring, and debugging Speedcore eFPGAs and Speedster FPGAs. ACE works in conjunction with third-party synthesis and simulation tools to provide a complete design environment for Achronix FPGAs

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