Product Briefs Version Released
Achronix Company Backgrounder (PB029)
Achronix Semiconductor Corporation is a privately held, fabless semiconductor corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market. Download
1.5 08/30/2019
HD1000 Development Kit (PB025)
The HD1000 development kit is optimized for development of networking and communication sub-systems — with 100 Gbps throughput, and offers the appropriate ports and memory capacity for these functions. Download
2.7 09/12/2016
PCIe Accelerator-6D Board (PB027)
The Achronix PCIe Accelerator-6D Board is the industry’s highest memory bandwidth, FPGA-based PCIe add-in card for high-speed acceleration applications. Download
1.6 06/20/2018
Speedcore eFPGA Product Brief (PB028)
Speedcore IP is embedded FPGA (eFPGA) that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements. Download
1.7 09/17/2019
Speedchip FPGA Chiplets (PB032)
Speedchip FPGA chiplets are optimized for embedding in advanced system-in-package (SiP) solutions such as 2.5D via silicon interposer or organic substrate. With Speedchip chiplets, customers define the functionality for their FPGA chiplet by specifying the number of LUTs, memory blocks, DSP blocks and I/O interfaces needed for their application. Achronix then develops the Speedchip chiplet tailored to the customer’s specification. Download
1.2 08/24/2018
Speedster22i HD FPGA Platform (PB024)
The Speedster22i HD FPGAs have a synchronous architecture and are built on Intel’s advanced 22nm 3-D Tri-Gate transistor technology. Targeted for high-bandwidth communication applications, Speedster22i HD FPGAs offer the combination of the highest density with the lowest power consumption. Download
2.7 06/12/2014
Speedster7t FPGAs Product Brief (PB033)
The Achronix Speedster®7t family is a revolutionary FPGA architecture highly optimized to meet the growing demands of AI/ML and high-bandwidth data acceleration applications. Specifically designed for these high-bandwidth workloads, the Speedster7t FPGA family features a revolutionary new 2D network on chip (NoC) and a high-density array of AI/ML optimized machine learning processors (MLP). Blending FPGA programmability with ASIC routing structures and compute engines, the Speedster7t family creates a new “FPGA+” class of technology. Download
1.2 07/15/2019
VectorPath S7t-VG6 Accelerater Card
Developed jointly with BittWare, the VectorPath™ S7t-VG6 accelerator card is designed to reduce time to market when developing high-performance compute and acceleration functions for artificial intelligence (AI), machine learning (ML), networking and data center applications. Download
1.0 10/29/2019
White Papers Version Released
2018 Ushers in a Renewed Push to the Edge (WP012)
The past decade has seen massive growth in centralized computing, with data processing flowing to the cloud to take advantage of low-cost dedicated data centers. It was a trend that seemed at odds with the general trend in computing — a trend that started with the mainframe but moved progressively towards ambient intelligence and the internet of things (IoT). As we move into 2018, this centralization is reaching its limit. The volume of data that will be needed to drive the next wave of applications is beginning to force a change in direction. Download
1.0 01/08/2018
Achieving ASIC Timing Closure with Speedcore eFPGAs (WP013)
Achronix's Speedcore eFPGA IP allows companies to embed a programmable logic fabric in their ASICs, delivering to end users the capability to modify or upgrade the functionality of an ASIC after being deployed in the field. This flexibility dramatically expands the solution space that can be served by the ASIC as it can be updated to support changing standards and algorithms. Timing closure is particularly challenging due to the fact that the eFPGA fabric may host any number of designs over the course of device operation. Each of those designs must work independently with the rest of the ASIC, and timing closure can only be said to have been met if all of the possible designs targeting the eFPGA fabric can meet timing. Download
1.0 07/17/2018
Chiplets – Taking SoC Design Where no Monolithic IC has Gone Before (WP016)
The chiplet movement is a reaction to the rapidly changing IC landscape and the current IC fabrication realities. Engineers are increasingly realizing that it makes little sense to integrate every IP block in a system on one piece of silicon if the fit is poor. There are many advantages with monolithic silicon integration, but those advantages are rapidly being outweighed by the economics of building advanced technology ICs. It is extremely expensive and time consuming to integrate, validate, and tapeout chips that can only be justified with high volume demand. More importantly, adding functionality or creating variations to support multiple end products increases die size and costs. Chiplets are becoming an alternative solution. Fortunately, the ecosystem for chiplets is quickly developing to provide companies a new tool to create highly optimized and cost effective solutions for their various end markets Download
1.1 04/04/2019
EFPGA Acceleration in SoCs — Understanding the Speedcore IP Design Process (WP008)
The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedded in an ASIC, are available to an ASIC development team either as products of the ACE design tools or as deliverables provided by Achronix. This methodology has already been proven in silicon and readily accommodates variations and preferences in company-specific ASIC development methodologies. Download
1.0 08/01/2017
Eight Benefits of Using an FPGA with an On-chip High-Speed Network (WP020)
Since the initial introduction of FPGAs decades ago, each new architecture has continued to employ a bit-wise routing structure. While this approach has been successful, the rise of high-speed communication standards has required ever increasing on-chip bus widths to be able to support these new data rates. Achronix's solution was to create a revolutionary 2D high-speed network on chip (NoC) on top of the traditional segmented FPGA routing structure for its new Speedster7t FPGA family. Download
1.1 12/05/2019
Embedded FPGA – a New System-Level Programming Paradigm (WP006)
The current public debate on the future of the semiconductor industry has turned to discussions about a growing selection of technologies that focuses instead on new system architectures and better use of available silicon through new concepts in circuit, device, and packaging design. The emergence of embedded FPGA is, in fact, not only essential at this juncture of the microelectronics history, but also inevitable. To understand this, a review of the history of FPGA technology is in order. Download
1.0 02/18/2017
Enhancing eFPGA Functionality with Speedcore Custom Blocks (WP009)
Achronix Speedcore™ eFPGA IP can be integrated in an SoC for high-performance, compute-intensive and realtime processing applications such as AI, automotive sensor fusion, network acceleration and wireless 5G. Speedcore eFPGA IP is a game-changer for SoC developers, allowing them to add flexibility to their products by including FPGA technology in their ASICs. For SoC development, companies specify the quantity and mix of lookup-table (LUT) logic, embedded memory blocks, and DSP blocks that best meets their needs. Along with these functions, Achronix now offers the ability for companies to define custom block functions, optimized for their application, that can also be included in the eFPGA fabric. Speedcore custom blocks increase die area efficiency, increase performance and lower power. Download
1.0 12/22/2017
Evaluating Speedcore IP For Your ASIC (WP007)
Phase zero is the beginning of a Speedcore design and how you begin matters. From a technical perspective, you will want to explore the possibilities to maximize the benefit of having your ASIC deployed with a Speedcore instance with a mix of resources well suited to your current and future programmed configurations. Achronix will help you along this road, providing support, training and feedback in employing tools, benchmarking designs and dealing with optimization issues. Download
1.0 08/04/2017
How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity (WP017)
Intelligent server adapters, or SmartNICs, boost server performance in cloud and private data centers by offloading network processing workloads and tasks from server CPUs. Offloading network processing to a SmartNIC is not a new concept — for example, there are NICs that offload some network-processing functions such as checksum computation and segmentation. However, the rapid explosion in data-center network traffic driven by software-defined networking (SDN), Open vSwitch (OVS), and network functions virtualization (NFV) demands a new class of NIC with even greater offload capabilities: the SmartNIC. Download
1.0 08/22/2019
How to Meet Power Performance and Cost for Autonomous Vehicle Systems using Speedcore eFPGAs (WP015)
In the advanced, fully autonomous, self-driving vehicles of the future, the existence of dozens and even hundreds of distributed CPUs and numerous other processing elements is assured. Peripheral sensor-fusion and other processing tasks can be served by ASICs, SoCs, or traditional FPGAs. But the introduction of embedded FPGA blocks such as Achronix's Speedcore eFPGA IP provides numerous system-design advantages in terms of shorter latency, more security, greater bandwidth, and better reliability that are simply not possible when using CPUs, GPUs, or even standalone FPGAs. Download
1.0 01/18/2019
Mine Cryptocurrencies Sooner, Faster, and Cheaper with Achronix Speedcore Embedded FPGAs (WP014)
New cryptocurrencies such as Monero introduce ASIC-resistance and memory-hardness to prevent ASICs from being built that give some operators a competitive mining advantage over others who do not have access to the same technology. This white paper discusses the relevant background and presents a solution based on Achronix Speedcore™ embedded FPGAs (eFPGAs), enabling users to regain a highly profitable advantage over competing solutions. Download
1.0 01/18/2019
Software-Defined Hardware Provides the Key to High-Performance Data Acceleration (WP019)
Across a wide range of industries, data acceleration is the key to building efficient, smart systems. A number of accelerator technologies have appeared to fill the gap that are based on custom silicon, graphics processors or dynamically reconfigurable hardware, but the key to their success is their ability to integrate into an environment where high throughput, low latency and ease of development are paramount requirements. A board-level platform developed jointly by Achronix and BittWare has been optimized for these applications, providing developers with a rapid path to deployment for high-throughput data acceleration. Download
1.0 11/13/2019
The Ideal Solution for AI Applications — Speedcore eFPGAs (WP011)
AI requires a careful balance of datapath performance, memory latency, and throughput that requires an approach based on pulling as much of the functionality as possible into an ASIC or SoC. But that single-chip device needs plasticity to be able to handle the changes in structure that are inevitable in machine-learning projects. Adding eFPGA technology provides the mixture of flexibility and support for custom logic that the market requires. Achronix provides not only the building blocks required for an AI-ready eFPGA solution, but also delivers a framework that supports design through to debug and test of the final application. Only Achronix Speedcore IP has the right mix of features for advanced AI that will support a new generation of real-time, self-learning systems. Download
1.0 12/22/2017
Using FPGAs to Accelerate Data Centers (WP005)
With the technology industry at a crossroads — the effective repeal of Moore's Law  — data centers have become the sweet spot of the technology sector, showing healthy revenue growth and attracting new system solutions in both hardware and software. Unlike the ethereal promise of upcoming wonders from AI, robotics and the IoT, data center growth and innovation is happening in the here and now, with an even brighter future ahead the moment other nascent markets emerge from their chrysalis with killer apps of their own. Download
1.0 06/14/2016
Datasheets and Tables Version Released
Speedcore Gen3 eFPGA Datasheet (DS003)
Achronix's Speedcore embedded FPGA architecture includes look-up-table, memory, and DSP building blocks that are designed in a modular structure which allows customers to define any quantity of resources required for their end system. Download
1.22 09/26/2019
Speedcore Gen4 eFPGA Datasheet (DS012)
Achronix's Speedcore Gen4 embedded FPGA (eFPGA) IP includes look-up-table, memory, DSP, and machine learning processor (MLP) building blocks. Each of these blocks are designed to be modular to allow customers to define any mix of resources required for their end system. Download
1.1 07/29/2019
Speedster22i HD1000 FPGA Datasheet (DS005)
Speedster22i HD1000 devices run at a maximum rate of 750 MHz and have an effective density of up to one million LUTs. Based on the Intel 22nm process, Speedster22i HD1000 devices are SRAM based and fully reconfigurable. Download
1.2 12/28/2017
Speedster22i HD1000 Pin Table
The pin tables (in Excel format) for the Speedster22i AC22IHD1000 in the FBGA2597 and FBGA1932 packages. Download
1.9 03/05/2015
Speedster7t FPGA Datasheet (DS015)
Achronix’s new 7nm Speedster®7t FPGA family is specifically designed to deliver extremely high performance for demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center. Download
0.92 06/24/2019
Speedster7t 7t1500 Pin Table
The pin tables (in Excel format) for the Speedster7t AC7t1500 in the FBGA2597 package. Download
1.6 06/19/2019
User Guides Version Released
All Achronix Devices
ACE Installation & Licensing Guide (UG002)
This guide covers software installation and licensing of ACE software under both Windows and Linux operating software. Download
2.2 06/25/2019
Bitstream Programming and Debug Interface User Guide (UG004)
The embedded programming and configuration logic in the Achronix core is designed to support a variety of programming and debugging options.This guide details those options and how to implement them at the board level, including using the Achronix STAPL player. Download
1.6 03/04/2019
Simulation User Guide (UG072)
The Achronix tool suite includes synthesis and place-and-route software that maps RTL designs (VHDL or Verilog) into Achronix devices. In addition to synthesis and place-and-route functions, the Achronix software tools flow also supports simulation at several flow steps (RTL, Synthesized Netlist, and Post Place-And-Routed Netlist). This guide covers the simulation flow for Achronix devices. Download
1.4 06/28/2018
Snapshot User Guide (UG016)
Snapshot is the real-time design debugging tool for Achronix FPGAs and cores. The Snapshot debugger, which is embedded in the ACE software, delivers a practical platform to observe the signals of a user's design in real-time. To use the Snapshot debugger, the Snapshot macro needs to be instantiated inside the user's RTL. After instantiating the macro and programming the device, the user will be able to debug the design through the Snapshot Debugger GUI within ACE, or via the run_snapshot TCL command API. Download
2.1 10/23/2018
Synthesis User Guide (UG018)
This user guide describes how to use Synplify Pro from Synopsys to synthesize a design and generate a netlist for implementation in Achronix devices. Suggested optimization techniques are also included. Download
1.4 06/10/2019
Speedcore eFPGAs
ACE User Guide (UG070)
This guide is a reference manual for the Achronix CAD Environment (ACE), used for placing, routing, configuring, and debugging Speedcore eFPGAs. ACE works in conjunction with third-party synthesis and simulation tools to provide a complete design environment for Achronix FPGAs. Download
7.2 06/06/2019
Speedcore ASIC Integration and Timing User Guide (UG064)
This guide details the design flow for integrating a Speedcore eFPGA into an ASIC, including closing timing across the boundary between the Speedcore instance and the surrounding host ASIC, along with how to perform full-chip simulation. Download
1.10 10/23/2018
Speedcore Clock and Reset Architecture User Guide (UG063)
This user guide details the clock structure for a Speedcore instance, covering the global core clock network, and interface clock networks. This guide also covers various clocking scenarios and their impact on timing closure. Download
1.6 10/23/2018
Speedcore Configuration User Guide (UG061)
During normal SoC operation, the Speedcore eFPGA core requires configuration by the end user. This guide covers the details of how to configure a Speedcore instance via JTAG, CPU, or serial flash interface. Also included are details on the Achronix Configuration Bus (ACB) interface that can be used to program configuration bits for ASIC IP surrounding the Speedcore eFPGA. Download
2.9 08/07/2019
Speedcore DFT and Test User Guide (UG067)
Design for test (DFT) is an important consideration for Speedcore eFPGAs from the perspective of both Achronix and the ASIC integrator. The programmable nature of Speedcore eFPGAs deliver the inherent benefit of being able to use the programmable logic fabric to test itself. This guide describes Speedcore eFPGAs from a testability perspective and outlines the general features and methodologies that Achronix uses to achieve the necessary coverage. Download
1.3 10/23/2018
Speedcore IP Component Library User Guide (UG065)
The Achronix Speedster16t macro cell library provides the user with building blocks that may be instantiated into the user’s design. In this guide, each library element entry describes the operation of the macro as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design. Download
1.16 04/05/2019
Speedcore Power Estimator User Guide (UG073)
The Achronix Speedcore Power Estimator tool provides a platform to calculate the power requirements for Achronix Speedcore eFPGAs. This user guide gives a detailed overview of the thermal and power needs depending on the device, environment and utilization of components in the design. Download
1.4 04/05/2019
Speedcore Power User Guide (UG066)
The power user guide covers the Achronix default power and signal integrity sign-off methodology with all relevant sign-off conditions. Also covered are power rail integration guidelines, power supply sequencing, power-on reset, and ESD guidelines. Download
1.8 10/17/2018
Speedcore Software Integration and Flow User Guide (UG062) Download 1.7 08/19/2018
Speedster7t FPGAs
Speedster7t Clock and Reset Architecture User Guide (UG083)
This document explains the architecture of the different clock networks in a Speedster7t FPGA, as well as information on how to use the clocks. It is intended to help designers understand and choose the best clocking options for their design on a Speedster7t FPGA. Download
1.0 05/22/2019
Speedster7t GDDR6 User Guide (UG091)
The Speedster7t FPGA device family provides multiple GDDR6 subsystems that enables the user to fully utilize the high-bandwidth efficiency of these interfaces for critical applications such as high-performance compute and machine learning systems. This guide provides the user with technical and architectural details of these subsystems, as well as details on how to configure and instantiate these subsystems in a design. Download
1.0 10/11/2019
Speedster7t IP Component Library User Guide (UG086)
The Achronix Speedster7t macro cell library provides the user with building blocks that may be instantiated into the user’s design. These macros provide access to low-level fabric primitives, complex I/O block, and higher level design components. Each library element entry describes the operation of the macro as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design. Download
0.91 10/10/2019
Speedster7t Machine Learning Processing User Guide (UG088)
The machine learning processing block (MLP) is an array of up to 32 multipliers, followed by an adder tree, an accumulator, and a rounding/saturation/normalize block.The MLP also includes two memory blocks, a BRAM72k and LRAM2k, that can be used individually or in conjunction with the array of multipliers. This guide provides the user with technical and usage details. Download
0.9 08/12/2019
Speedster7t Network on Chip User Guide (UG089)
The Speedster7t FPGA family of devices has a network hierarchy that enables extremely high-speed dataflow between the FPGA core and the interfaces around the periphery, as well as between logic within the FPGA itself. This on-chip network hierarchy supports a cross-sectional bidirectional bandwidth of 20 Tbps, supporting a multitude of interface protocols. This guide provides the user with an architectural overview the this network on chip (NoC) plus usage details. Download
1.0 09/19/2019
Speedster7t Pin Connectivity User Guide (UG084)
This user guide lists each of the I/O pin groups available in the Speedster7t 7t1500 device, their functionality and recommended connection guidelines. Refer to the Power User Guide for detailed description on the power/gnd pins. Download
1.1 06/11/2019
Speedster7t Power User Guide
This guide describes the different power supplies that are required for the Speedster7t 7t1500 device and voltage tolerance levels for each of them. Also included are the connection guidelines for each of the power rails and recommendations for the power supply network sharing schemes at the board level. Download
1.0 07/15/2019
Speedster7t Reference Designs User Guide (UG085)
This guide describes a collection of reference designs that demonstrate some of the advanced features of the Speedster7t FPGA family. They are primarily focused on the machine learning processor (MLP) block which is tightly coupled with a block memory (BRAM). These designs are provided "as-is", with no warranty with regard to fitness of purpose, or direct applicability to a users solution. Download
1.1 09/16/2019
Speedster22i FPGAs
ACE Timing Constraints User Guide (UG053) Download 1.0 04/17/2015
ACE User Guide for Speedster22i FPGAs (UG001) Download 7.2 06/06/2019
ACX-KIT-HD1000-100G Development Kit QuickStart Guide (UG045) Download 1.3 01/03/2015
ACX-KIT-HD1000-100G Development Kit User Guide (UG034) Download 1.12 06/27/2016
PCIe Accelerator-6D Card User Guide (UG074) Download 1.1 03/23/2017
PCIe Accelerator-6D Card Quick Start User Guide (UG055) Download 1.2 11/09/2016
Speedster22i 10/40/100 Gigabit Ethernet User Guide (UG029) Download 1.7 01/20/2017
Speedster22i Capacitor User Guide (UG051) Download 1.0 04/10/2015
Speedster22i Configuration User Guide (UG033) Download 1.3 03/07/2016
Speedster22i Clock and Reset Networks User Guide (UG027) Download 1.8 05/16/2016
Speedster22i DDR3 User Guide (UG031) Download 3.0 11/19/2018
Speedster22i Interlaken User Guide (UG032) Download 1.2 05/15/2014
Speedster22i Macro Cell Library (UG021) Download 1.10 04/21/2016
Speedster22i Memory PHY User Guide (UG043) Download 1.0 04/26/2016
Speedster22i Pin Connections and Power Supply Sequencing User Guide (UG042) Download 1.14 03/07/2016
Speedster22i Power Estimator Tool User Guide (UG054) Download 1.0 07/28/2016
Speedster22i SerDes User Guide (UG028) Download 2.2 11/24/2015
Speedster22i sBus Interface User Guide (UG047) Download 1.0 10/24/2016
Speedster22i PCI Express User Guide (UG030) Download 2.1 05/22/2016

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