Product Briefs Version Released
Achronix Company Backgrounder (PB029)
Achronix Semiconductor Corporation is a privately held, fabless semiconductor corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market. Download
1.2 06/19/2018
HD1000 Development Kit (PB025)
The HD1000 development kit is optimized for development of networking and communication sub-systems — with 100 Gbps throughput, and offers the appropriate ports and memory capacity for these functions. Download
2.7 09/12/2016
PCIe Accelerator-6D Board (PB027)
The Achronix PCIe Accelerator-6D Board is the industry’s highest memory bandwidth, FPGA-based PCIe add-in card for high-speed acceleration applications. Download
1.6 06/20/2018
Speedcore eFPGA Product Brief (PB028)
Speedcore IP is embedded FPGA (eFPGA) that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements. Download
1.5 07/14/2018
Speedchip FPGA Chiplets (PB032)
Speedchip FPGA chiplets are optimized for embedding in advanced system-in-package (SiP) solutions such as 2.5D via silicon interposer or organic substrate. With Speedchip chiplets, customers define the functionality for their FPGA chiplet by specifying the number of LUTs, memory blocks, DSP blocks and I/O interfaces needed for their application. Achronix then develops the Speedchip chiplet tailored to the customer’s specification. Download
1.2 08/24/2018
Speedster22i HD FPGA Platform (PB024)
The Speedster22i HD FPGAs have a synchronous architecture and are built on Intel’s advanced 22nm 3-D Tri-Gate transistor technology. Targeted for high-bandwidth communication applications, Speedster22i HD FPGAs offer the combination of the highest density with the lowest power consumption. Download
2.7 06/12/2014
White Papers Version Released
2018 Ushers in a Renewed Push to the Edge (WP012)
The past decade has seen massive growth in centralized computing, with data processing flowing to the cloud to take advantage of low-cost dedicated data centers. It was a trend that seemed at odds with the general trend in computing — a trend that started with the mainframe but moved progressively towards ambient intelligence and the internet of things (IoT). As we move into 2018, this centralization is reaching its limit. The volume of data that will be needed to drive the next wave of applications is beginning to force a change in direction. Download
1.0 01/08/2018
Achieving ASIC Timing Closure with Speedcore eFPGAs (WP013)
Achronix's Speedcore eFPGA IP allows companies to embed a programmable logic fabric in their ASICs, delivering to end users the capability to modify or upgrade the functionality of an ASIC after being deployed in the field. This flexibility dramatically expands the solution space that can be served by the ASIC as it can be updated to support changing standards and algorithms. Timing closure is particularly challenging due to the fact that the eFPGA fabric may host any number of designs over the course of device operation. Each of those designs must work independently with the rest of the ASIC, and timing closure can only be said to have been met if all of the possible designs targeting the eFPGA fabric can meet timing. Download
1.0 07/17/2018
Enhancing eFPGA Functionality with Speedcore Custom Blocks (WP009)
Achronix Speedcore™ eFPGA IP can be integrated in an SoC for high-performance, compute-intensive and realtime processing applications such as AI, automotive sensor fusion, network acceleration and wireless 5G. Speedcore eFPGA IP is a game-changer for SoC developers, allowing them to add flexibility to their products by including FPGA technology in their ASICs. For SoC development, companies specify the quantity and mix of lookup-table (LUT) logic, embedded memory blocks, and DSP blocks that best meets their needs. Along with these functions, Achronix now offers the ability for companies to define custom block functions, optimized for their application, that can also be included in the eFPGA fabric. Speedcore custom blocks increase die area efficiency, increase performance and lower power. Download
1.0 12/22/2017
EFPGA Acceleration in SoCs — Understanding the Speedcore IP Design Process (WP008)
The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedded in an ASIC, are available to an ASIC development team either as products of the ACE design tools or as deliverables provided by Achronix. This methodology has already been proven in silicon and readily accommodates variations and preferences in company-specific ASIC development methodologies. Download
1.0 08/01/2017
Embedded FPGA – a New System-Level Programming Paradigm (WP006)
The current public debate on the future of the semiconductor industry has turned to discussions about a growing selection of technologies that focuses instead on new system architectures and better use of available silicon through new concepts in circuit, device, and packaging design. The emergence of embedded FPGA is, in fact, not only essential at this juncture of the microelectronics history, but also inevitable. To understand this, a review of the history of FPGA technology is in order. Download
1.0 02/18/2017
Evaluating Speedcore IP For Your ASIC (WP007)
Phase zero is the beginning of a Speedcore design and how you begin matters. From a technical perspective, you will want to explore the possibilities to maximize the benefit of having your ASIC deployed with a Speedcore instance with a mix of resources well suited to your current and future programmed configurations. Achronix will help you along this road, providing support, training and feedback in employing tools, benchmarking designs and dealing with optimization issues. Download
1.0 08/04/2017
The Ideal Solution for AI Applications — Speedcore eFPGAs (WP011)
AI requires a careful balance of datapath performance, memory latency, and throughput that requires an approach based on pulling as much of the functionality as possible into an ASIC or SoC. But that single-chip device needs plasticity to be able to handle the changes in structure that are inevitable in machine-learning projects. Adding eFPGA technology provides the mixture of flexibility and support for custom logic that the market requires. Achronix provides not only the building blocks required for an AI-ready eFPGA solution, but also delivers a framework that supports design through to debug and test of the final application. Only Achronix Speedcore IP has the right mix of features for advanced AI that will support a new generation of real-time, self-learning systems. Download
1.0 12/22/2017
Speedcore eFPGA in Automotive Intelligence Applications (WP010)
Whether an automobile is a piloted vehicle of the early 2020s, or a future autonomous vehicle of level 3 and above, the need for hardware acceleration in networked transportation system is skyrocketing. Today, attention is rapidly shifting to decentralized automotive intelligence, in which complex cameras with associated vision systems, sensor subnetworks with sensor-hub architectures from the IoT world, and additional subnetworks for IVI, ADAS, and drive-train/power train subnetworks, all collaborate to implement autonomous vehicle functions. In order to optimize real estate and power efficiency, the customer-configurable capabilities offered by integrating Speedcore™ embedded FPGA (eFPGA) IP into an SoC represents an optimal choice compared to fixed-function SoCs or traditional FPGAs in implementing rapidly-shifting co-processing in future automotive platforms. Download
1.0 12/04/2017
Using FPGAs to Accelerate Data Centers (WP005)
With the technology industry at a crossroads — the effective repeal of Moore's Law  — data centers have become the sweet spot of the technology sector, showing healthy revenue growth and attracting new system solutions in both hardware and software. Unlike the ethereal promise of upcoming wonders from AI, robotics and the IoT, data center growth and innovation is happening in the here and now, with an even brighter future ahead the moment other nascent markets emerge from their chrysalis with killer apps of their own. Download
1.0 06/14/2016
Datasheets and Tables Version Released
Speedcore eFPGA Datasheet (DS003)
Achronix's Speedcore embedded FPGA architecture includes look-up-table, memory, and DSP building blocks that are designed in a modular structure which allows customers to define any quantity of resources required for their end system. Download
1.20 05/22/2018
Speedster22i HD1000 FPGA Datasheet (DS005)
Speedster22i HD1000 devices run at a maximum rate of 750 MHz and have an effective density of up to one million LUTs. Based on the Intel 22nm process, Speedster22i HD1000 devices are SRAM based and fully reconfigurable. Download
1.2 12/28/2017
Speedster22i HD1000 Pin Table
The pin tables (in Excel format) for the Speedster22i AC22IHD1000 in the FBGA2597 and FBGA1932 packages. Download
1.9 03/05/2015
User Guides Version Released
All Achronix Devices
ACE Installation & Licensing Guide (UG002)
This guide covers software installation and licensing of ACE software under both Windows and Linux operating software. Download
2.1 10/23/2018
Bitstream Programming and Debug Interface User Guide (UG004)
The embedded programming and configuration logic in the Achronix core is designed to support a variety of programming and debugging options.This guide details those options and how to implement them at the board level, including using the Achronix STAPL player. Download
1.5 07/21/2017
Simulation User Guide (UG072)
The Achronix tool suite includes synthesis and place-and-route software that maps RTL designs (VHDL or Verilog) into Achronix devices. In addition to synthesis and place-and-route functions, the Achronix software tools flow also supports simulation at several flow steps (RTL, Synthesized Netlist, and Post Place-And-Routed Netlist). This guide covers the simulation flow for Achronix devices. Download
1.3 03/27/2018
Snapshot User Guide (UG016)
Snapshot is the real-time design debugging tool for Achronix FPGAs and cores. The Snapshot debugger, which is embedded in the ACE software, delivers a practical platform to observe the signals of a user's design in real-time. To use the Snapshot debugger, the Snapshot macro needs to be instantiated inside the user's RTL. After instantiating the macro and programming the device, the user will be able to debug the design through the Snapshot Debugger GUI within ACE, or via the run_snapshot TCL command API. Download
2.1 10/23/2018
Speedcore eFPGAs
ACE User Guide for Speedcore eFPGAs (UG070)
This guide is a reference manual for the Achronix CAD Environment (ACE), used for placing, routing, configuring, and debugging Speedcore eFPGAs. ACE works in conjunction with third-party synthesis and simulation tools to provide a complete design environment for Achronix FPGAs. Download
3.0 08/19/2018
Speedcore ASIC Integration and Timing User Guide (UG064)
This guide details the design flow for integrating a Speedcore eFPGA into an ASIC, including closing timing across the boundary between the Speedcore instance and the surrounding host ASIC, along with how to perform full-chip simulation. Download
1.10 10/23/2018
Speedcore Clock and Reset Architecture User Guide (UG063)
This user guide details the clock structure for a Speedcore instance, covering the global core clock network, and interface clock networks. This guide also covers various clocking scenarios and their impact on timing closure. Download
1.6 10/23/2018
Speedcore Configuration User Guide (UG061)
During normal SoC operation, the Speedcore eFPGA core requires configuration by the end user. This guide covers the details of how to configure a Speedcore instance via JTAG, CPU, or serial flash interface. Also included are details on the Achronix Configuration Bus (ACB) interface that can be used to program configuration bits for ASIC IP surrounding the Speedcore eFPGA. Download
2.8 11/14/2018
Speedcore DFT and Test User Guide (UG067)
Design for test (DFT) is an important consideration for Speedcore eFPGAs from the perspective of both Achronix and the ASIC integrator. The programmable nature of Speedcore eFPGAs deliver the inherent benefit of being able to use the programmable logic fabric to test itself. This guide describes Speedcore eFPGAs from a testability perspective and outlines the general features and methodologies that Achronix uses to achieve the necessary coverage. Download
1.3 10/23/2018
Speedcore IP Component Library User Guide (UG065)
The Achronix Speedster16t macro cell library provides the user with building blocks that may be instantiated into the user’s design. In this guide, each library element entry describes the operation of the macro as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design. Download
1.14 08/19/2018
Speedcore Power Estimator User Guide (UG073)
The Achronix Speedcore Power Estimator tool provides a platform to calculate the power requirements for Achronix Speedcore eFPGAs. This user guide gives a detailed overview of the thermal and power needs depending on the device, environment and utilization of components in the design. Download
1.3 11/07/2018
Speedcore Power User Guide (UG066)
The power user guide covers the Achronix default power and signal integrity sign-off methodology with all relevant sign-off conditions. Also covered are power rail integration guidelines, power supply sequencing, power-on reset, and ESD guidelines. Download
1.8 10/17/2018
Speedcore Software Integration and Flow User Guide (UG062) Download 1.7 08/19/2018
Speedcore Synthesis User Guide (UG071) Download 1.3 10/01/2018
Speedster22i FPGAs
ACE User Guide (UG001) Download 6.0.0 01/05/2016
ACE Timing Constraints User Guide (UG053) Download 1.0 04/17/2015
ACX-KIT-HD1000-100G Development Kit QuickStart Guide (UG045) Download 1.3 01/03/2015
ACX-KIT-HD1000-100G Development Kit User Guide (UG034) Download 1.12 06/27/2016
PCIe Accelerator-6D Card Quick Start User Guide (UG055) Download 1.2 11/09/2016
PCIe Accelerator-6D Card User Guide (UG074) Download 1.1 03/23/2017
Speedster22i 10/40/100 Gigabit Ethernet User Guide (UG029) Download 1.7 01/20/2017
Speedster22i Capacitor User Guide (UG051) Download 1.0 04/10/2015
Speedster22i Configuration User Guide (UG033) Download 1.3 03/07/2016
Speedster22i Clock and Reset Networks User Guide (UG027) Download 1.8 05/16/2016
Speedster22i DDR3 User Guide (UG031) Download 3.0 11/19/2018
Speedster22i Interlaken User Guide (UG032) Download 1.2 05/15/2014
Speedster22i Macro Cell Library (UG021) Download 1.10 04/21/2016
Speedster22i Memory PHY User Guide (UG043) Download 1.0 04/26/2016
Speedster22i Pin Connections and Power Supply Sequencing User Guide (UG042) Download 1.14 03/07/2016
Speedster22i Power Estimator Tool User Guide (UG054) Download 1.0 07/28/2016
Speedster22i SerDes User Guide (UG028) Download 2.2 11/24/2015
Speedster22i sBus Interface User Guide (UG047) Download 1.0 10/24/2016
Speedster22i PCI Express User Guide (UG030) Download 2.1 05/22/2016
Synthesis User Guide for Speedster22i HD Devices (UG018) Download 1.1 04/15/2013

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