Documentation

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Title Description Version Released Date Document File
An FPGA-Based Solution for a Graph Neural Network Accelerator (WP024)

Thanks to the rise of big data and the rapid increase in computing power, machine learning technology has experienced revolutionary development in recent years. Machine learning tasks such as image classification, speech recognition, and natural language processing, operate on Euclidean data with a certain size, dimension, and an orderly arrangement. However, in many realistic scenarios, data is represented by complex non-Euclidean data such as graphs. In this context, many new graph-based machine learning algorithm, or graph neural networks (GNNs), are constantly emerging in academia and industry.

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The AI Evolution Calls for Adaptable Inferencing Platforms (WP023)

Deep learning's demand for computing power is growing at an incredible rate, accelerating recently from doubling every year to doubling every three months. Increasing the capacity of deep neural network (DNN) models has shown improvements across a wide range of areas ranging from natural language processing to image processing. This growth calls for the adoption of customized architectures that squeeze the greatest amount of performance out of each transistor available.

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FPGAs for Advanced Video Processing Solutions (WP022)

While the performance of an ASIC is typically high enough for broadcast-quality video processing, it supports only the feature set conceived of at design time and is not field upgradable. A CPU is the most flexible and easiest to design; however, clock frequencies have plateaued, and the era of dramatic improvements in performance are over. FPGAs represent a good balance between performance and flexibility for this class of applications.

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FPGAs Enable the Next Generation of Communication and Networking Solutions (WP021)

Communications and networking systems that extend from the edges of the 5G network to the switches inside data centers are placing extreme pressure on the ability of silicon to support the computational and data-transfer rates they require. Traditionally programmable logic provided the best mixture of flexibility and speed for these systems, but has been challenged in recent years by the increase in speed. Through the inclusion of an innovative, multilevel network on chip that allows data to be streamed easily around the device without impacting the FPGA fabric, the Speedster7t architecture ensures all device resources are used to their full potential.

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Eight Benefits of Using an FPGA with an On-chip High-Speed Network (WP020)

Since the initial introduction of FPGAs decades ago, each new architecture has continued to employ a bit-wise routing structure. While this approach has been successful, the rise of high-speed communication standards has required ever increasing on-chip bus widths to be able to support these new data rates. Achronix's solution was to create a revolutionary 2D high-speed network on chip (NoC) on top of the traditional segmented FPGA routing structure for its new Speedster7t FPGA family.

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Title Description Version Released Date Document File
Repeatability in ACE (AN012)

One of the desired requirements of any FPGA design tool is the ability to reproduce the exact same results every time the tool is run under the same conditions — a requirement refereed to as repeatability. The ACE placer and router are deterministic, delivering 100% repeatability.

1.2 Repeatability_in_ACE_AN012.pdf
Measuring Accurate Toggle Rates

When calculating dynamic power for a design, one input to any power estimation is the toggle rate of the signals. In most circumstances, the value used will be one of the industry standards of either 12.5% or 25% — values derived from a wide range of designs.

1.0 Measuring_Accurate_Toggle_Rates_AN010.pdf
Formal Verification in the ACE Flow (AN013)

This application note covers the formal verification support available in the ACE environment. ACE currently is capable of supporting formal equivalency checking in its design flow, enabling the user to verify the synthesized netlist against the output at the different stages in the ACE flow.

1.0 Formal_Verification_in_the_ACE_Flow_AN013.pdf
Routing Reset Signals on Speedcore eFPGAs (AN007)

In FPGA design, reset signals can sometimes have a significant effect on the overall quality of timing or routing results. Generally it is recommended to reduce the number of logic elements that need to be reset by taking advantage of initial values and coding in such a way that reset is only needed on a few end points.

1.2 Routing_Reset_Signals_on_Speedcore_eFPGAs_AN007.pdf
Clock Design Planning for Speedcore eFPGAs (AN011)

Speedcore eFPGAs have a robust clocking architecture. While some designs only use a single main clock, others can have complicated clocking schemes. It is important for designers to understand the different types of clocks available in the Speedcore architecture, and how to get the best design out of the clocking resources available.

1.0 Clock_Design_Planning_for_Speedcore_eFPGAs_AN011.pdf
Title Description Version Released Date Document File
Speedster7t GPIO User Guide (UG112)

This document describes the Speedster7t FPGA GPIO pins, their various features, how to configure them, any design considerations to be taken into account, and the tools required to implement them.

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Speedcore Component Library User Guide (UG065)

This library describes the programmable fabric silicon elements which may be instantiated into a custom design.

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Snapshot User Guide (UG016)

Snapshot is the real-time design debugging tool for Achronix FPGAs and cores. This guide details the setup and operation of the Snapshot feature using a simple reference design.

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Speedster7t 2D Network on Chip User Guide (UG089)

The Speedster7t FPGA family of devices has a network hierarchy that enables extremely high-speed dataflow between the FPGA core and the interfaces around the periphery, as well as between logic within the FPGA itself. This on-chip network hierarchy supports a cross-sectional bidirectional bandwidth of 20 Tbps. It supports a multitude of interface protocols including GDDR6, DDR4/5, 400G Ethernet, and PCI Express Gen5 data streams, while greatly simplifying access to memory and high-speed protocols. Achronix's two-dimensional network on chip (2D NoC) provides for read/write transactions throughout the device, as well as specialized support for 400G Ethernet streams in selected columns. The features of the 2D NoC described in this user guide generally pertain to the entire Speedster7t family of devices. In order to help users understand specific connections and features of the 2D NoC, this user guide focuses on the 2D NoC as implemented in the AC7t1500 device.

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Speedster7t Ethernet User Guide (UG097)

Speedster7t devices include high-speed Ethernet interfaces, which can support a wide variety of Ethernet packet protocols and speeds of up to 400 Gbps per channel. These Ethernet interfaces are paired with latest generation SerDes which individually support 100 Gbps data rates. With eight of these SerDes per Ethernet interface, each interface can support 2× 400 Gbps Ethernet IP channels.

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