Documentation

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Title Description Version Released Date Document File
EFPGA Acceleration in SoCs — Understanding the Speedcore IP Design Process (WP008)

The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedded in an ASIC, are available to an ASIC development team either as products of the ACE design tools or as deliverables provided by Achronix. This methodology has already been proven in silicon and readily accommodates variations and preferences in company-specific ASIC development methodologies.

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Embedded FPGA – a New System-Level Programming Paradigm (WP006)

The current public debate on the future of the semiconductor industry has turned to discussions about a growing selection of technologies that focuses instead on new system architectures and better use of available silicon through new concepts in circuit, device, and packaging design. The emergence of embedded FPGA is, in fact, not only essential at this juncture of the microelectronics history, but also inevitable. To understand this, a review of the history of FPGA technology is in order.

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Using FPGAs to Accelerate Data Centers (WP005)

With the technology industry at a crossroads — the effective repeal of Moore's Law  — data centers have become the sweet spot of the technology sector, showing healthy revenue growth and attracting new system solutions in both hardware and software. Unlike the ethereal promise of upcoming wonders from AI, robotics and the IoT, data center growth and innovation is happening in the here and now, with an even brighter future ahead the moment other nascent markets emerge from their chrysalis with killer apps of their own.

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Title Description Version Released Date Document File
Coding Guidelines for Speedcore eFPGAs (AN003)

In order to obtain the best quality of results (QoR) when targeting any design to an FPGA, it is sometimes necessary to structure the RTL and constraints to take best advantage of the underlying FPGA architecture and the built-in features of the tool chain.

2.0 Coding_Guidelines_for_Speedcore_eFPGAs_AN003.pdf
Routing Reset Signals on Speedcore eFPGAs (AN007)

In FPGA design, reset signals can sometimes have a significant effect on the overall quality of timing or routing results. Generally it is recommended to reduce the number of logic elements that need to be reset by taking advantage of initial values and coding in such a way that reset is only needed on a few end points.

1.2 Routing_Reset_Signals_on_Speedcore_eFPGAs_AN007.pdf
Measuring Accurate Toggle Rates

When calculating dynamic power for a design, one input to any power estimation is the toggle rate of the signals. In most circumstances, the value used will be one of the industry standards of either 12.5% or 25% — values derived from a wide range of designs.

1.0 Measuring_Accurate_Toggle_Rates_AN010.pdf
Formal Verification in the ACE Flow (AN013)

This application note covers the formal verification support available in the ACE environment. ACE currently is capable of supporting formal equivalency checking in its design flow, enabling the user to verify the synthesized netlist against the output at the different stages in the ACE flow.

1.0 Formal_Verification_in_the_ACE_Flow_AN013.pdf
Clock Design Planning for Speedcore eFPGAs (AN011)

Speedcore eFPGAs have a robust clocking architecture. While some designs only use a single main clock, others can have complicated clocking schemes. It is important for designers to understand the different types of clocks available in the Speedcore architecture, and how to get the best design out of the clocking resources available.

1.0 Clock_Design_Planning_for_Speedcore_eFPGAs_AN011.pdf
Title Description Version Released Date Document File
Speedster7t DDR User Guide (UG096)

The Achronix Speedster7t FPGA family provides DDR subsystems that enable the user to fully utilize the low latency and high-bandwidth efficiency of these interfaces for critical applications such as high-performance compute and machine learning systems. The DDR subsystem supports memory devices and features compliant with JEDEC Standard JESD79-4B.

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Speedster7t Network on Chip User Guide (UG089)

The Speedster7t FPGA family of devices has a network hierarchy that enables extremely high-speed dataflow between the FPGA core and the interfaces around the periphery, as well as between logic within the FPGA itself. This on-chip network hierarchy supports a cross-sectional bidirectional bandwidth of 20 Tbps. It supports a multitude of interface protocols including GDDR6, DDR4/5, 400G Ethernet, and PCI Express Gen5 data streams, while greatly simplifying access to memory and high-speed protocols. Achronix's network on chip (NoC) provides for read/write transactions throughout the device, as well as specialized support for 400G Ethernet streams in selected columns. The features of the NoC described in this user guide generally pertain to the entire Speedster7t family of devices. In order to help users understand specific connections and features of the NoC, this user guide focuses on the NoC as implemented in the AC7t1500 device. 

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ACE User Guide for Speedster22i FPGAs (UG001)

This guide is a reference manual for the Achronix CAD Environment (ACE), used for placing, routing, configuring, and debugging Achronix FPGAs. ACE works in conjunction with third-party synthesis and simulation tools to provide a complete design environment for Achronix FPGAs.

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Speedster7t Machine Learning Processing User Guide (UG088)

The machine learning processing block (MLP) is an array of up to 32 multipliers, followed by an adder tree, an accumulator, and a rounding/saturation/normalize block.The MLP also includes two memory blocks, a BRAM72k and LRAM2k, that can be used individually or in conjunction with the array of multipliers. The number of multipliers available varies with the bit width of each operand and the total width of input data. When the MLP is used in conjunction with a BRAM72k, the amount of data inputs to the MLP block increases along with the number of multipliers available. 

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Speedcore Configuration User Guide (UG061)

During normal SoC operation, the Speedcore eFPGA core requires configuration by the end user. This guide covers the details of how to configure a Speedcore instance via JTAG, CPU, or serial flash interface. Also included are details on the Achronix Configuration Bus (ACB) interface that can be used to program configuration bits for ASIC IP surrounding the Speedcore eFPGA.

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