Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
Mine Cryptocurrencies Sooner, Faster, and Cheaper with Achronix Speedcore Embedded FPGAs (WP014)

New cryptocurrencies such as Monero introduce ASIC-resistance and memory-hardness to prevent ASICs from being built that give some operators a competitive mining advantage over others who do not have access to the same technology. This white paper discusses the relevant background and presents a solution based on Achronix Speedcore™ embedded FPGAs (eFPGAs), enabling users to regain a highly profitable advantage over competing solutions.

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How to Meet Power Performance and Cost for Autonomous Vehicle Systems using Speedcore eFPGAs (WP015)

In the advanced, fully autonomous, self-driving vehicles of the future, the existence of dozens and even hundreds of distributed CPUs and numerous other processing elements is assured. Peripheral sensor-fusion and other processing tasks can be served by ASICs, SoCs, or traditional FPGAs. But the introduction of embedded FPGA blocks such as Achronix's Speedcore eFPGA IP provides numerous system-design advantages in terms of shorter latency, more security, greater bandwidth, and better reliability that are simply not possible when using CPUs, GPUs, or even standalone FPGAs.

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Achieving ASIC Timing Closure with Speedcore eFPGAs (WP013)

Achronix's Speedcore eFPGA IP allows companies to embed a programmable logic fabric in their ASICs, delivering to end users the capability to modify or upgrade the functionality of an ASIC after being deployed in the field. This flexibility dramatically expands the solution space that can be served by the ASIC as it can be updated to support changing standards and algorithms. Timing closure is particularly challenging due to the fact that the eFPGA fabric may host any number of designs over the course of device operation. Each of those designs must work independently with the rest of the ASIC, and timing closure can only be said to have been met if all of the possible designs targeting the eFPGA fabric can meet timing.

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2018 Ushers in a Renewed Push to the Edge (WP012)

The past decade has seen massive growth in centralized computing, with data processing flowing to the cloud to take advantage of low-cost dedicated data centers. It was a trend that seemed at odds with the general trend in computing — a trend that started with the mainframe but moved progressively towards ambient intelligence and the internet of things (IoT). As we move into 2018, this centralization is reaching its limit. The volume of data that will be needed to drive the next wave of applications is beginning to force a change in direction.

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The Ideal Solution for AI Applications — Speedcore eFPGAs (WP011)

AI requires a careful balance of datapath performance, memory latency, and throughput that requires an approach based on pulling as much of the functionality as possible into an ASIC or SoC. But that single-chip device needs plasticity to be able to handle the changes in structure that are inevitable in machine-learning projects. Adding eFPGA technology provides the mixture of flexibility and support for custom logic that the market requires. Achronix provides not only the building blocks required for an AI-ready eFPGA solution, but also delivers a framework that supports design through to debug and test of the final application. Only Achronix Speedcore IP has the right mix of features for advanced AI that will support a new generation of real-time, self-learning systems.

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Title Description Version Released Date Document File
ACE ECO Flow Guide (AN015)

This tutorial serves as an introduce to the ACE engineering change order (ECO) suite — a set of Tcl commands that can add or remove instances, nets, pin connections, and more from a placed-and-routed design.

1.0 ACE_ECO_Flow_Guide_AN015.pdf
Pipelining the CPU Interface (AN016)

A Speedcore instance hosted in an SoC supports three different configuration modes: CPU, serial flash and JTAG. In CPU mode, an external CPU acts as the master and controls the programming operations for the Speedcore eFPGA, and offers a high-speed method for loading configuration data.

1.0 Pipelining_the_CPU_Interface_AN016.pdf
Repeatability in ACE (AN012)

One of the desired requirements of any FPGA design tool is the ability to reproduce the exact same results every time the tool is run under the same conditions — a requirement refereed to as repeatability. The ACE placer and router are deterministic, delivering 100% repeatability.

1.2 Repeatability_in_ACE_AN012.pdf
Coding Guidelines for Speedcore eFPGAs (AN003)

In order to obtain the best quality of results (QoR) when targeting any design to an FPGA, it is sometimes necessary to structure the RTL and constraints to take best advantage of the underlying FPGA architecture and the built-in features of the tool chain.

2.0 Coding_Guidelines_for_Speedcore_eFPGAs_AN003.pdf
Routing Reset Signals on Speedcore eFPGAs (AN007)

In FPGA design, reset signals can sometimes have a significant effect on the overall quality of timing or routing results. Generally it is recommended to reduce the number of logic elements that need to be reset by taking advantage of initial values and coding in such a way that reset is only needed on a few end points.

1.2 Routing_Reset_Signals_on_Speedcore_eFPGAs_AN007.pdf
Title Description Version Released Date Document File
Speedster7t Power User Guide (UG087)

This document describes the different power supplies that are required for the Speedster7t 7t1500 device and voltage tolerance levels for each of them. Also included are the connection guidelines for each of the power rails and recommendations for the power supply network sharing schemes at the board level.

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Speedcore Configuration User Guide (UG061)

During normal SoC operation, the Speedcore eFPGA core requires configuration by the end user. This guide covers the details of how to configure a Speedcore instance via JTAG, CPU, or serial flash interface. Also included are details on the Achronix Configuration Bus (ACB) interface that can be used to program configuration bits for ASIC IP surrounding the Speedcore eFPGA.

2.11 Download
Speedcore Software Integration and Flow User Guide (UG062)

Speedcore Software Integration and Flow User Guide (UG062)

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Speedster7t Ethernet User Guide (UG097)

Speedster7t devices include high-speed Ethernet interfaces, which can support a wide variety of Ethernet packet protocols and speeds of up to 400 Gbps per channel. These Ethernet interfaces are paired with latest generation SerDes which individually support 100 Gbps data rates. With eight of these SerDes per Ethernet interface, each interface can support 2× 400 Gbps Ethernet IP channels.

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Speedcore Clock and Reset Architecture User Guide (UG063)

This user guide details the clock structure for a Speedcore instance, covering the global core clock network, and interface clock networks. This guide also covers various clocking scenarios and their impact on timing closure.

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