Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
FPGAs Enable the Next Generation of Communication and Networking Solutions (WP021)

Communications and networking systems that extend from the edges of the 5G network to the switches inside data centers are placing extreme pressure on the ability of silicon to support the computational and data-transfer rates they require. Traditionally programmable logic provided the best mixture of flexibility and speed for these systems, but has been challenged in recent years by the increase in speed. Through the inclusion of an innovative, multilevel network on chip that allows data to be streamed easily around the device without impacting the FPGA fabric, the Speedster7t architecture ensures all device resources are used to their full potential.

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Eight Benefits of Using an FPGA with an On-chip High-Speed Network (WP020)

Since the initial introduction of FPGAs decades ago, each new architecture has continued to employ a bit-wise routing structure. While this approach has been successful, the rise of high-speed communication standards has required ever increasing on-chip bus widths to be able to support these new data rates. Achronix's solution was to create a revolutionary 2D high-speed network on chip (NoC) on top of the traditional segmented FPGA routing structure for its new Speedster7t FPGA family.

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How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity (WP017)

Intelligent server adapters, or SmartNICs, boost server performance in cloud and private data centers by offloading network processing workloads and tasks from server CPUs. Offloading network processing to a SmartNIC is not a new concept — for example, there are NICs that offload some network-processing functions such as checksum computation and segmentation. However, the rapid explosion in data-center network traffic driven by software-defined networking (SDN), Open vSwitch (OVS), and network functions virtualization (NFV) demands a new class of NIC with even greater offload capabilities: the SmartNIC.

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Mine Cryptocurrencies Sooner, Faster, and Cheaper with Achronix Speedcore Embedded FPGAs (WP014)

New cryptocurrencies such as Monero introduce ASIC-resistance and memory-hardness to prevent ASICs from being built that give some operators a competitive mining advantage over others who do not have access to the same technology. This white paper discusses the relevant background and presents a solution based on Achronix Speedcore™ embedded FPGAs (eFPGAs), enabling users to regain a highly profitable advantage over competing solutions.

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How to Meet Power Performance and Cost for Autonomous Vehicle Systems using Speedcore eFPGAs (WP015)

In the advanced, fully autonomous, self-driving vehicles of the future, the existence of dozens and even hundreds of distributed CPUs and numerous other processing elements is assured. Peripheral sensor-fusion and other processing tasks can be served by ASICs, SoCs, or traditional FPGAs. But the introduction of embedded FPGA blocks such as Achronix's Speedcore eFPGA IP provides numerous system-design advantages in terms of shorter latency, more security, greater bandwidth, and better reliability that are simply not possible when using CPUs, GPUs, or even standalone FPGAs.

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Title Description Version Released Date Document File
Migrating to Achronix eFPGA Technology (AN014)

Many users transitioning to Achronix eFPGA technology will be familiar with existing FPGA solutions from other vendors. Although Achronix technology and tools are similar to existing FPGA technology and tools, there are some differences. Understanding these differences are needed to achieve the very best performance and quality of results (QoR).

 1.1 Migrating_to_Achronix_eFPGA_Technology_AN014.pdf
Using Encrypted Source Files with ACE (AN008)

Designers need a way to protect their source IP, and that is often achieved by way of encrypted RTL. Achronix's tool flow using ACE and SynplifyPro supports the use of encrypted IP to enable protection of all or part of an IP's RTL.

 1.0 Using_Encrypted_Source_Files_with_ACE_AN008.pdf
ACE ECO Flow Guide (AN015)

This tutorial serves as an introduce to the ACE engineering change order (ECO) suite — a set of Tcl commands that can add or remove instances, nets, pin connections, and more from a placed-and-routed design.

 1.0 ACE_ECO_Flow_Guide_AN015.pdf
Pipelining the CPU Interface (AN016)

A Speedcore instance hosted in an SoC supports three different configuration modes: CPU, serial flash and JTAG. In CPU mode, an external CPU acts as the master and controls the programming operations for the Speedcore eFPGA, and offers a high-speed method for loading configuration data.

 1.0 Pipelining_the_CPU_Interface_AN016.pdf
Repeatability in ACE (AN012)

One of the desired requirements of any FPGA design tool is the ability to reproduce the exact same results every time the tool is run under the same conditions — a requirement refereed to as repeatability. The ACE placer and router are deterministic, delivering 100% repeatability.

 1.2 Repeatability_in_ACE_AN012.pdf
Title Description Version Released Date Document File
JTAG Configuration User Guide (UG004)

This User Guide details Speedster FPGA bitstream configuration specifically using the JTAG interface.

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Speedster7t Pin Connectivity User Guide (UG084)

This user guide lists each of the I/O pin groups available in the Speedster7t 7t1500 device, their functionality and recommended connection guidelines.

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Speedster7t Configuration User Guide (UG094)

At startup, Speedster7t FPGAs require configuration by the end user via a bitstream. This bitstream can be programmed through one of four available interfaces in the FPGA configuration unit (FCU), which is logic that controls the configuration process of the Speedster7t FPGA.

 1.0.4 Download
Speedster7t Power User Guide (UG087)

This document describes the different power supplies that are required for the Speedster7t 7t1500 device and voltage tolerance levels for each of them. Also included are the connection guidelines for each of the power rails and recommendations for the power supply network sharing schemes at the board level.

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Speedster7t Component Library User Guide (UG086)

The Achronix Speedster7t component library provides the user with building blocks that may be instantiated into the user’s design. These components provide access to low-level fabric primitives, complex I/O blocks, and higher level design components. Each library element entry describes the operation of the component as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design.

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