Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
Evaluating Speedcore IP For Your ASIC (WP007)

Phase zero is the beginning of a Speedcore design and how you begin matters. From a technical perspective, you will want to explore the possibilities to maximize the benefit of having your ASIC deployed with a Speedcore instance with a mix of resources well suited to your current and future programmed configurations. Achronix will help you along this road, providing support, training and feedback in employing tools, benchmarking designs and dealing with optimization issues.

1.00 Download
EFPGA Acceleration in SoCs — Understanding the Speedcore IP Design Process (WP008)

The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedded in an ASIC, are available to an ASIC development team either as products of the ACE design tools or as deliverables provided by Achronix. This methodology has already been proven in silicon and readily accommodates variations and preferences in company-specific ASIC development methodologies.

1.00 Download
Embedded FPGA – a New System-Level Programming Paradigm (WP006)

The current public debate on the future of the semiconductor industry has turned to discussions about a growing selection of technologies that focuses instead on new system architectures and better use of available silicon through new concepts in circuit, device, and packaging design. The emergence of embedded FPGA is, in fact, not only essential at this juncture of the microelectronics history, but also inevitable. To understand this, a review of the history of FPGA technology is in order.

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Using FPGAs to Accelerate Data Centers (WP005)

With the technology industry at a crossroads — the effective repeal of Moore's Law  — data centers have become the sweet spot of the technology sector, showing healthy revenue growth and attracting new system solutions in both hardware and software. Unlike the ethereal promise of upcoming wonders from AI, robotics and the IoT, data center growth and innovation is happening in the here and now, with an even brighter future ahead the moment other nascent markets emerge from their chrysalis with killer apps of their own.

1.00 Download
Title Description Version Released Date Document File
Migrating to Achronix FPGA Technology

Many users transitioning to Achronix FPGA and eFPGA technology will be familiar with existing FPGA solutions from other vendors. Although Achronix technology and tools are similar to existing FPGA technology and tools, there are some differences. Understanding these differences are needed to achieve the very best performance and quality of results (QoR).

1.00 Migrating_to_Achronix_FPGA_Technology_AN014.pdf
Clock Design Planning for Speedcore eFPGAs

Speedcore eFPGAs have a robust clocking architecture. While some designs only use a single main clock, others can have complicated clocking schemes. It is important for designers to understand the different types of clocks available in the Speedcore architecture, and how to get the best design out of the clocking resources available.

1.00 Clock_Design_Planning_for_Speedcore_eFPGAs_AN011.pdf
Speedcore User Interface Timing Sign-off Methodology

Timing sign-off between the host ASIC and the Speedcore boundary is one of the most crucial steps in ensuring proper integration of a Speedcore instance into a customer's SoC.

1.00 Speedcore_User_Interface_Timing_Sign-off_Methodology_AN009.pdf
Coding Guidelines for Speedcore eFPGAs

In order to obtain the best quality of results (QoR) when targeting any design to an FPGA, it is sometimes necessary to structure the RTL and constraints to take best advantage of the underlying FPGA architecture and the built-in features of the tool chain.

2.00 Coding_Guidelines_for_Speedcore_eFPGAs_AN003.pdf
Routing Reset Signals on Speedcore eFPGAs

In FPGA design, reset signals can sometimes have a significant effect on the overall quality of timing or routing results. Generally it is recommended to reduce the number of logic elements that need to be reset by taking advantage of initial values and coding in such a way that reset is only needed on a few end points.

1.20 Routing_Reset_Signals_on_Speedcore_eFPGAs_AN007.pdf
Title Description Version Released Date Document File
Speedcore Configuration User Guide (UG061)

During normal SoC operation, the Speedcore eFPGA core requires configuration by the end user. This guide covers the details of how to configure a Speedcore instance via JTAG, CPU, or serial flash interface. Also included are details on the Achronix Configuration Bus (ACB) interface that can be used to program configuration bits for ASIC IP surrounding the Speedcore eFPGA.

2.90 Download
Speedster7t Power User Guide

This document describes the different power supplies that are required for the Speedster7t 7t1500 device and voltage tolerance levels for each of them. Also included are the connection guidelines for each of the power rails and recommendations for the power supply network sharing schemes at the board level.

1.00 Download
Speedster7t Pin Connectivity User Guide (UG084)

This user guide lists each of the I/O pin groups available in the Speedster7t 7t1500 device, their functionality and recommended connection guidelines. Refer to the Power User Guide for detailed description on the power/gnd pins

1.10 Download
Synthesis User Guide (UG018)

This user guide describes how to use Synplify Pro from Synopsys to synthesize a design and generate a netlist for implementation in Achronix devices. Suggested optimization techniques are also included.

1.40 Download
ACE User Guide (UG001)

ACE User Guide (UG001)

7.20 Download