Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
Data Orchestration Supports the Next Advance in AI (WP025)

Artificial intelligence (AI) and machine learning (ML) technologies now power a rapidly expanding range of product and applications from deeply embedded systems to hyperscale data-center deployments. Although there is a huge degree of diversity in the hardware designs supporting these applications, all require hardware acceleration. Data orchestration encompasses the pre- and post-processing operations that ensure the data seen by a machine learning engine arrives at an optimal speed and in the most suitable form for efficient processing.

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FPGAs and eFPGAs Accelerate ML Inference at the Edge (WP026)

With the rapid proliferation of Internet-of-Things (IoT) and billions of connected devices, there is a paradigm shift taking place where big data is not only being processed in the core data center but also at the network edge. Field Programmable Gate Arrays (FPGAs), sitting at the intersection of performance and flexibility, are a promising solution for deep learning edge inference applications.

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Achronix FPGAs Optimize AI in Industry 4.0 and 5.0 (WP027)

Industry has come a long way over in the last three hundred years. Machines were first introduced in the 1700s, mainly water and steam driven, introducing the Industrial Revolution in the late 1700s. Automation and computer technology would enter the picture in the late 1960's, paving the way for the eventual automation, artificial intelligence (AI) and networked solutions of today. Although it might appear that humans are no longer in the picture, Industry 5.0 is bringing us full circle by combining the precision and efficiency of robotic systems, driven largely by AI, with the ingenuity and real-time thought of the human mind — all leading to more optimal manufacturing environments.

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Reduce Speech Transcription Costs by up to 90% with CAI (WP030)

Conversational artificial intelligence (CAI) uses deep learning (DL), a subset of machine learning (ML), to automate speech recognition, natural language processing and text to speech using machines. Achronix and Myrtle.ai are teaming up to deliver an ASR platform consisting of a 200W, x16 PCIe Gen4-based accelerator card and the associated software which together can sustain up to 4000 RTS concurrently, processing up to 1 million five-minute transcriptions per 24-hour period — reducing costs by as much as 90% versus cloud-based APIs.

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Enabling the Next Generation of 5G Platforms (WP029)

Radio access networks (RANs) and associated core network hierarchy, which link end-user equipment to both the central telecom network and the cloud, are essential in building ubiquitous cellular connectivity to expand the number and breadth of use cases that can be supported by the technology. This paper outlines the current status of 5G standards and rollout, summarizes the new use cases 5G RANs need to support and examines the standards evolution to support higher bandwidth and additional use cases. Finally, it also explains how Achronix FPGA technology can be utilized by developers to meet the fundamental challenge facing them.

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Title Description Version Released Date Document File
PCIe Enumeration of Speedster7t FPGAs (AN027)

This Application Note provides the steps to attain enumeration from a non-enumerated device with a PCIe interface and from an already enumerated device.

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Title Description Version Released Date Document File
Speedster7t Clock and Reset Architecture User Guide (UG083)

This document explains the architecture of the different clock networks in a Speedster7t FPGA and and provides information on how to use the clocks.

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Speedster7t Ethernet User Guide (UG097)

Speedster7t devices include high-speed Ethernet interfaces, which can support a wide variety of Ethernet packet protocols and speeds of up to 400 Gbps per channel. These Ethernet interfaces are paired with latest generation SerDes which individually support 100 Gbps data rates. With eight of these SerDes per Ethernet interface, each interface can support 2× 400 Gbps Ethernet IP channels.

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Speedster7t GDDR6 User Guide (UG091)

The Speedster7t FPGA family provides multiple GDDR6 subsystems enabling full utilization of the high-bandwidth efficiency of these interfaces for critical applications. This guide provides the details for implementing the GDDR6 IP in custom designs.

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Speedster7t 2D Network on Chip User Guide (UG089)

The Speedster7t FPGA family of devices has a network hierarchy that enables extremely high-speed dataflow between the FPGA core and the interfaces around the periphery, as well as between logic within the FPGA itself. This on-chip network hierarchy supports a cross-sectional bidirectional bandwidth of 20 Tbps. It supports a multitude of interface protocols including GDDR6, DDR4/5, 400G Ethernet, and PCI Express Gen5 data streams, while greatly simplifying access to memory and high-speed protocols. Achronix's two-dimensional network on chip (2D NoC) provides for read/write transactions throughout the device, as well as specialized support for 400G Ethernet streams in selected columns. The features of the 2D NoC described in this user guide generally pertain to the entire Speedster7t family of devices. In order to help users understand specific connections and features of the 2D NoC, this user guide focuses on the 2D NoC as implemented in the AC7t1500 device.

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Snapshot User Guide (UG016)

Snapshot is the real-time design debugging tool for Achronix FPGAs and cores. This guide details the setup and operation of the Snapshot feature using a simple reference design.

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