Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
Using FPGAs to Accelerate Data Centers (WP005)

With the technology industry at a crossroads — the effective repeal of Moore's Law  — data centers have become the sweet spot of the technology sector, showing healthy revenue growth and attracting new system solutions in both hardware and software. Unlike the ethereal promise of upcoming wonders from AI, robotics and the IoT, data center growth and innovation is happening in the here and now, with an even brighter future ahead the moment other nascent markets emerge from their chrysalis with killer apps of their own.

1.00 Download
Embedded FPGA – a New System-Level Programming Paradigm (WP006)

The current public debate on the future of the semiconductor industry has turned to discussions about a growing selection of technologies that focuses instead on new system architectures and better use of available silicon through new concepts in circuit, device, and packaging design. The emergence of embedded FPGA is, in fact, not only essential at this juncture of the microelectronics history, but also inevitable. To understand this, a review of the history of FPGA technology is in order.

1.00 Download
EFPGA Acceleration in SoCs — Understanding the Speedcore IP Design Process (WP008)

The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedded in an ASIC, are available to an ASIC development team either as products of the ACE design tools or as deliverables provided by Achronix. This methodology has already been proven in silicon and readily accommodates variations and preferences in company-specific ASIC development methodologies.

1.00 Download
Evaluating Speedcore IP For Your ASIC (WP007)

Phase zero is the beginning of a Speedcore design and how you begin matters. From a technical perspective, you will want to explore the possibilities to maximize the benefit of having your ASIC deployed with a Speedcore instance with a mix of resources well suited to your current and future programmed configurations. Achronix will help you along this road, providing support, training and feedback in employing tools, benchmarking designs and dealing with optimization issues.

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The Ideal Solution for AI Applications — Speedcore eFPGAs (WP011)

AI requires a careful balance of datapath performance, memory latency, and throughput that requires an approach based on pulling as much of the functionality as possible into an ASIC or SoC. But that single-chip device needs plasticity to be able to handle the changes in structure that are inevitable in machine-learning projects. Adding eFPGA technology provides the mixture of flexibility and support for custom logic that the market requires. Achronix provides not only the building blocks required for an AI-ready eFPGA solution, but also delivers a framework that supports design through to debug and test of the final application. Only Achronix Speedcore IP has the right mix of features for advanced AI that will support a new generation of real-time, self-learning systems.

1.00 Download
Title Description Version Released Date Document File
Speedster22i HD1000 Pin Table

The pin tables (in Excel format) for the Speedster22i AC22IHD1000 in the FBGA2597 and FBGA1932 packages.

1.90 Download
Speedster22i HD1000 FPGA Datasheet (DS005)

Speedster22i HD1000 devices run at a maximum rate of 750 MHz and have an effective density of up to one million LUTs. Based on the Intel 22nm process, Speedster22i HD1000 devices are SRAM based and fully reconfigurable.

1.20 Download
Speedcore eFPGA Datasheet (DS003)

Achronix's Speedcore embedded FPGA architecture includes look-up-table, memory, and DSP building blocks that are designed in a modular structure which allows customers to define any quantity of resources required for their end system.

1.20 Download
Speedcore Gen4 eFPGA Datasheet (DS012)

Achronix's Speedcore Gen4 embedded FPGA (eFPGA) IP includes look-up-table, memory, DSP, and machine learning processor (MLP) building blocks. Each of these blocks are designed to be modular to allow customers to define any mix of resources required for their end system.

1.10 Download
Speedster7t 7t1500 Pin Table

The pin tables (in Excel format) for the Speedster7t AC7t1500 in the FBGA2597 package.

1.80 Download
Title Description Version Released Date Document File
Clock Design Planning for Speedcore eFPGAs

Speedcore eFPGAs have a robust clocking architecture. While some designs only use a single main clock, others can have complicated clocking schemes. It is important for designers to understand the different types of clocks available in the Speedcore architecture, and how to get the best design out of the clocking resources available.

1.00 Clock_Design_Planning_for_Speedcore_eFPGAs_AN011.pdf
Speedcore User Interface Timing Sign-off Methodology

Timing sign-off between the host ASIC and the Speedcore boundary is one of the most crucial steps in ensuring proper integration of a Speedcore instance into a customer's SoC.

1.00 Speedcore_User_Interface_Timing_Sign-off_Methodology_AN009.pdf
Coding Guidelines for Speedcore eFPGAs

In order to obtain the best quality of results (QoR) when targeting any design to an FPGA, it is sometimes necessary to structure the RTL and constraints to take best advantage of the underlying FPGA architecture and the built-in features of the tool chain.

2.00 Coding_Guidelines_for_Speedcore_eFPGAs_AN003.pdf
Routing Reset Signals on Speedcore eFPGAs

In FPGA design, reset signals can sometimes have a significant effect on the overall quality of timing or routing results. Generally it is recommended to reduce the number of logic elements that need to be reset by taking advantage of initial values and coding in such a way that reset is only needed on a few end points.

1.20 Routing_Reset_Signals_on_Speedcore_eFPGAs_AN007.pdf
Measuring Accurate Toggle Rates

When calculating dynamic power for a design, one input to any power estimation is the toggle rate of the signals. In most circumstances, the value used will be one of the industry standards of either 12.5% or 25% — values derived from a wide range of designs.

1.00 Measuring_Accurate_Toggle_Rates_AN010.pdf
Title Description Version Released Date Document File
Speedster22i HD FPGA Platform (PB024)

The Speedster22i HD FPGAs have a synchronous architecture and are built on Intel’s advanced 22nm 3-D Tri-Gate transistor technology. Targeted for high-bandwidth communication applications, Speedster22i HD FPGAs offer the combination of the highest density with the lowest power consumption.

2.70 Download
HD1000 Development Kit (PB025)

The HD1000 development kit is optimized for development of networking and communication sub-systems — with 100 Gbps throughput, and offers the appropriate ports and memory capacity for these functions.

2.70 Download
PCIe Accelerator-6D Board (PB027)

The Achronix PCIe Accelerator-6D Board is the industry’s highest memory bandwidth, FPGA-based PCIe add-in card for high-speed acceleration applications.

1.60 Download
Speedcore eFPGA Product Brief (PB028)

Speedcore IP is embedded FPGA (eFPGA) that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements.

1.50 Download
Speedchip FPGA Chiplets (PB032)

Speedchip FPGA chiplets are optimized for embedding in advanced system-in-package (SiP) solutions such as 2.5D via silicon interposer or organic substrate. With Speedchip chiplets, customers define the functionality for their FPGA chiplet by specifying the number of LUTs, memory blocks, DSP blocks and I/O interfaces needed for their application. Achronix then develops the Speedchip chiplet tailored to the customer’s specification.

1.20 Download
Title Description Version Released Date Document File
Speedster22i Interlaken User Guide (UG032)

Speedster22i Interlaken User Guide (UG032)

1.20 Download
ACX-KIT-HD1000-100G Development Kit QuickStart Guide (UG045)

ACX-KIT-HD1000-100G Development Kit QuickStart Guide (UG045)

1.30 Download
Speedster22i Capacitor User Guide (UG051)

Speedster22i Capacitor User Guide (UG051)

1.00 Download
Speedster22i Configuration User Guide (UG033)

Speedster22i Configuration User Guide (UG033)

1.30 Download
Speedster22i Pin Connections and Power Supply Sequencing User Guide (UG042)

Speedster22i Pin Connections and Power Supply Sequencing User Guide (UG042)

1.10 Download