Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

Select the individual tabs below to browse through each type of documentation. Or use the filter to only see documentation related to your product of interest.

Some documents are restricted (denoted by the lock symbol in the download button) and require a support portal account to access the download. To download a restricted document, enter your support portal account credentials when prompted. Don't have a support portal account? Register for an account here: Achronix Support Account Registration

Title Description Version Released Date Document File
Using FPGAs to Accelerate Data Centers (WP005)

With the technology industry at a crossroads — the effective repeal of Moore's Law  — data centers have become the sweet spot of the technology sector, showing healthy revenue growth and attracting new system solutions in both hardware and software. Unlike the ethereal promise of upcoming wonders from AI, robotics and the IoT, data center growth and innovation is happening in the here and now, with an even brighter future ahead the moment other nascent markets emerge from their chrysalis with killer apps of their own.

1.0 Download
Embedded FPGA – a New System-Level Programming Paradigm (WP006)

The current public debate on the future of the semiconductor industry has turned to discussions about a growing selection of technologies that focuses instead on new system architectures and better use of available silicon through new concepts in circuit, device, and packaging design. The emergence of embedded FPGA is, in fact, not only essential at this juncture of the microelectronics history, but also inevitable. To understand this, a review of the history of FPGA technology is in order.

1.0 Download
EFPGA Acceleration in SoCs — Understanding the Speedcore IP Design Process (WP008)

The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedded in an ASIC, are available to an ASIC development team either as products of the ACE design tools or as deliverables provided by Achronix. This methodology has already been proven in silicon and readily accommodates variations and preferences in company-specific ASIC development methodologies.

1.0 Download
Evaluating Speedcore IP For Your ASIC (WP007)

Phase zero is the beginning of a Speedcore design and how you begin matters. From a technical perspective, you will want to explore the possibilities to maximize the benefit of having your ASIC deployed with a Speedcore instance with a mix of resources well suited to your current and future programmed configurations. Achronix will help you along this road, providing support, training and feedback in employing tools, benchmarking designs and dealing with optimization issues.

1.0 Download
Enhancing eFPGA Functionality with Speedcore Custom Blocks (WP009)

Achronix Speedcore™ eFPGA IP can be integrated in an SoC for high-performance, compute-intensive and realtime processing applications such as AI, automotive sensor fusion, network acceleration and wireless 5G. Speedcore eFPGA IP is a game-changer for SoC developers, allowing them to add flexibility to their products by including FPGA technology in their ASICs. For SoC development, companies specify the quantity and mix of lookup-table (LUT) logic, embedded memory blocks, and DSP blocks that best meets their needs. Along with these functions, Achronix now offers the ability for companies to define custom block functions, optimized for their application, that can also be included in the eFPGA fabric. Speedcore custom blocks increase die area efficiency, increase performance and lower power.

1.0 Download
Title Description Version Released Date Document File
Speedster22i HD1000 Pin Table

The pin tables (in Excel format) for the Speedster22i AC22IHD1000 in the FBGA2597 and FBGA1932 packages.

1.9 Download
Speedster22i HD1000 FPGA Datasheet (DS005)

Speedster22i HD1000 devices run at a maximum rate of 750 MHz and have an effective density of up to one million LUTs. Based on the Intel 22nm process, Speedster22i HD1000 devices are SRAM based and fully reconfigurable.

1.2 Download
Speedcore Gen4 eFPGA Datasheet (DS012)

Achronix's Speedcore Gen4 embedded FPGA (eFPGA) IP includes look-up-table, memory, DSP, and machine learning processor (MLP) building blocks. Each of these blocks are designed to be modular to allow customers to define any mix of resources required for their end system.

1.1 Download
Speedster7t 7t1500 Pin Table

The pin tables (in Excel format) for the Speedster7t AC7t1500 in the FBGA2597 package.

1.8 Download
Speedcore Gen3 eFPGA Datasheet (DS003)

Achronix's Speedcore embedded FPGA architecture includes look-up-table, memory, and DSP building blocks that are designed in a modular structure which allows customers to define any quantity of resources required for their end system.

1.2 Download
Title Description Version Released Date Document File
Device Binning Methodologies (AN005)

The manufacturing process for any silicon device inevitably has variations, whether those are in the thickness of a substrate or track, the purity of a conductor, position of the die on the wafer, or one of a myriad of many other physical effects.

1.0 Device_Binning_Methodologies_AN005.pdf
Speedcore User Interface Timing Sign-off Methodology (AN009)

Timing sign-off between the host ASIC and the Speedcore boundary is one of the most crucial steps in ensuring proper integration of a Speedcore instance into a customer's SoC.

1.0 Speedcore_User_Interface_Timing_Sign-off_Methodology_AN009.pdf
Coding Guidelines for Speedcore eFPGAs (AN003)

In order to obtain the best quality of results (QoR) when targeting any design to an FPGA, it is sometimes necessary to structure the RTL and constraints to take best advantage of the underlying FPGA architecture and the built-in features of the tool chain.

2.0 Coding_Guidelines_for_Speedcore_eFPGAs_AN003.pdf
Routing Reset Signals on Speedcore eFPGAs (AN007)

In FPGA design, reset signals can sometimes have a significant effect on the overall quality of timing or routing results. Generally it is recommended to reduce the number of logic elements that need to be reset by taking advantage of initial values and coding in such a way that reset is only needed on a few end points.

1.2 Routing_Reset_Signals_on_Speedcore_eFPGAs_AN007.pdf
Measuring Accurate Toggle Rates

When calculating dynamic power for a design, one input to any power estimation is the toggle rate of the signals. In most circumstances, the value used will be one of the industry standards of either 12.5% or 25% — values derived from a wide range of designs.

1.0 Measuring_Accurate_Toggle_Rates_AN010.pdf
Title Description Version Released Date Document File
Speedster22i HD FPGA Platform (PB024)

The Speedster22i HD FPGAs have a synchronous architecture and are built on Intel’s advanced 22nm 3-D Tri-Gate transistor technology. Targeted for high-bandwidth communication applications, Speedster22i HD FPGAs offer the combination of the highest density with the lowest power consumption.

2.7 Download
HD1000 Development Kit (PB025)

The HD1000 development kit is optimized for development of networking and communication sub-systems — with 100 Gbps throughput, and offers the appropriate ports and memory capacity for these functions.

2.7 Download
Speedcore eFPGA Test Chip Evaluation Board (PB030)

The Speedcore eFPGA evaluation board from Achronix contains the 16-nm Speedcore eFPGA test chip. The evaluation board’s Speedcore test chip has been customized with the right blend of resources such as LUTs, BRAMs, DSP64s, DFFs and a number of I/O so as to provide an optimum programmable platform for demonstrating, evaluating and testing Achronix’s Speedcore technology.

1.0 Download
PCIe Accelerator-6D Board (PB027)

The Achronix PCIe Accelerator-6D Board is the industry’s highest memory bandwidth, FPGA-based PCIe add-in card for high-speed acceleration applications.

1.6 Download
Speedster7t FPGAs Product Brief (PB033)

The Achronix Speedster®7t family is a revolutionary FPGA architecture highly optimized to meet the growing demands of AI/ML and high-bandwidth data acceleration applications. Specifically designed for these high-bandwidth workloads, the Speedster7t FPGA family features a revolutionary new 2D network on chip (NoC) and a high-density array of AI/ML optimized machine learning processors (MLP). Blending FPGA programmability with ASIC routing structures and compute engines, the Speedster7t family creates a new “FPGA+” class of technology.

1.2 Download
Title Description Version Released Date Document File
Speedster22i Interlaken User Guide (UG032)

Speedster22i Interlaken User Guide (UG032)

1.2 Download
ACX-KIT-HD1000-100G Development Kit QuickStart Guide (UG045)

ACX-KIT-HD1000-100G Development Kit QuickStart Guide (UG045)

1.3 Download
Speedster22i Capacitor User Guide (UG051)

Speedster22i Capacitor User Guide (UG051)

1.0 Download
Speedster22i Configuration User Guide (UG033)

Speedster22i Configuration User Guide (UG033)

1.3 Download
Speedster22i Pin Connections and Power Supply Sequencing User Guide (UG042)

Speedster22i Pin Connections and Power Supply Sequencing User Guide (UG042)

1.1 Download