Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
Using FPGAs to Accelerate Data Centers (WP005)

With the technology industry at a crossroads — the effective repeal of Moore's Law  — data centers have become the sweet spot of the technology sector, showing healthy revenue growth and attracting new system solutions in both hardware and software. Unlike the ethereal promise of upcoming wonders from AI, robotics and the IoT, data center growth and innovation is happening in the here and now, with an even brighter future ahead the moment other nascent markets emerge from their chrysalis with killer apps of their own.

1.0 Download
Embedded FPGA – a New System-Level Programming Paradigm (WP006)

The current public debate on the future of the semiconductor industry has turned to discussions about a growing selection of technologies that focuses instead on new system architectures and better use of available silicon through new concepts in circuit, device, and packaging design. The emergence of embedded FPGA is, in fact, not only essential at this juncture of the microelectronics history, but also inevitable. To understand this, a review of the history of FPGA technology is in order.

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EFPGA Acceleration in SoCs — Understanding the Speedcore IP Design Process (WP008)

The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedded in an ASIC, are available to an ASIC development team either as products of the ACE design tools or as deliverables provided by Achronix. This methodology has already been proven in silicon and readily accommodates variations and preferences in company-specific ASIC development methodologies.

1.0 Download
Evaluating Speedcore IP For Your ASIC (WP007)

Phase zero is the beginning of a Speedcore design and how you begin matters. From a technical perspective, you will want to explore the possibilities to maximize the benefit of having your ASIC deployed with a Speedcore instance with a mix of resources well suited to your current and future programmed configurations. Achronix will help you along this road, providing support, training and feedback in employing tools, benchmarking designs and dealing with optimization issues.

1.0 Download
The Ideal Solution for AI Applications — Speedcore eFPGAs (WP011)

AI requires a careful balance of datapath performance, memory latency, and throughput that requires an approach based on pulling as much of the functionality as possible into an ASIC or SoC. But that single-chip device needs plasticity to be able to handle the changes in structure that are inevitable in machine-learning projects. Adding eFPGA technology provides the mixture of flexibility and support for custom logic that the market requires. Achronix provides not only the building blocks required for an AI-ready eFPGA solution, but also delivers a framework that supports design through to debug and test of the final application. Only Achronix Speedcore IP has the right mix of features for advanced AI that will support a new generation of real-time, self-learning systems.

1.0 Download
Title Description Version Released Date Document File
Speedster7t 7t1500 Pin Table

The pin tables (in Excel format) for the Speedster7t AC7t1500 in the FBGA2597 package.

2.0 Download
Speedcore eFPGA Datasheet (DS012)

Achronix Speedcore embedded FPGA (eFPGA) IP includes look-up-table, memory, and DSP blocks. Each of these blocks are designed to be modular to allow customers to define any mix of resources required for their end system.

2.0.1 Download
Speedster7t FPGA Datasheet (DS015)

Achronix’s new 7nm Speedster7t FPGA family is specifically designed to deliver extremely high performance for demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center.

1.5 Download
Title Description Version Released Date Document File
Device Binning Methodologies (AN005)

The manufacturing process for any silicon device inevitably has variations, whether those are in the thickness of a substrate or track, the purity of a conductor, position of the die on the wafer, or one of a myriad of many other physical effects.

1.0 Device_Binning_Methodologies_AN005.pdf
Clock Design Planning for Speedcore eFPGAs (AN011)

Speedcore eFPGAs have a robust clocking architecture. While some designs only use a single main clock, others can have complicated clocking schemes. It is important for designers to understand the different types of clocks available in the Speedcore architecture, and how to get the best design out of the clocking resources available.

1.0 Clock_Design_Planning_for_Speedcore_eFPGAs_AN011.pdf
Coding Guidelines for Speedcore eFPGAs (AN003)

In order to obtain the best quality of results (QoR) when targeting any design to an FPGA, it is sometimes necessary to structure the RTL and constraints to take best advantage of the underlying FPGA architecture and the built-in features of the tool chain.

2.0 Coding_Guidelines_for_Speedcore_eFPGAs_AN003.pdf
Routing Reset Signals on Speedcore eFPGAs (AN007)

In FPGA design, reset signals can sometimes have a significant effect on the overall quality of timing or routing results. Generally it is recommended to reduce the number of logic elements that need to be reset by taking advantage of initial values and coding in such a way that reset is only needed on a few end points.

1.2 Routing_Reset_Signals_on_Speedcore_eFPGAs_AN007.pdf
Measuring Accurate Toggle Rates

When calculating dynamic power for a design, one input to any power estimation is the toggle rate of the signals. In most circumstances, the value used will be one of the industry standards of either 12.5% or 25% — values derived from a wide range of designs.

1.0 Measuring_Accurate_Toggle_Rates_AN010.pdf
Title Description Version Released Date Document File
Speedcore eFPGA Test Chip Evaluation Board (PB030)

The Speedcore eFPGA evaluation board from Achronix contains the 16-nm Speedcore eFPGA test chip. The evaluation board’s Speedcore test chip has been customized with the right blend of resources such as LUTs, BRAMs, DSP64s, DFFs and a number of I/O so as to provide an optimum programmable platform for demonstrating, evaluating and testing Achronix’s Speedcore technology.

1.0 Download
Maximize Hardware Assurance Using Embedded FPGAs (PB035)

Implementing a secure IP solution when developing a custom ASIC involves overcoming many risks along the development, manufacturing and supply chain flow. Hardware assurance continues to become more critical for military and defense applications as worldwide threats increase. By using an eFPGA IP solution to store mission critical IP, supply chain security is greatly simplified compared to the traditional ASIC design flow.

1.0 Download
Speedcore eFPGA Product Brief (PB028)

Speedcore IP is embedded FPGA (eFPGA) that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements.

1.8 Download
VectorPath S7t-VG6 Accelerator Card

Developed jointly with BittWare, the VectorPath™ S7t-VG6 accelerator card is designed to reduce time to market when developing high-performance compute and acceleration functions for artificial intelligence (AI), machine learning (ML), networking and data center applications.

14 Download
Achronix Tool Suite (PB002)

The Achronix Tool Suite works in conjunction with industry-standard synthesis tools, allowing FPGA designers (for both standalone and embedded) to easily map their designs into Achronix FPGA technology. Achronix provides ACE together with an Achronix-optimized version of Synplify Pro from Synopsys, the industry standard for producing high-performance and cost-effective FPGA designs.

5.4 Download
Title Description Version Released Date Document File
Speedcore Software Integration and Flow User Guide (UG062)

Speedcore Software Integration and Flow User Guide (UG062)

1.7 Download
Speedcore Power User Guide (UG066)

The power user guide covers the Achronix default power and signal integrity sign-off methodology with all relevant sign-off conditions. Also covered are power rail integration guidelines, power supply sequencing, power-on reset, and ESD guidelines.

1.8 Download
Snapshot User Guide (UG016)

Snapshot is the real-time design debugging tool for Achronix FPGAs and cores. The Snapshot debugger, which is embedded in the ACE software, delivers a practical platform to observe the signals of a user's design in real-time. To use the Snapshot debugger, the Snapshot macro needs to be instantiated inside the user's RTL. After instantiating the macro and programming the device, the user will be able to debug the design through the Snapshot Debugger GUI within ACE, or via the run_snapshotTCL command API.

2.1 Download
Speedcore ASIC Integration and Timing User Guide (UG064)

This guide details the design flow for integrating a Speedcore eFPGA into an ASIC, including closing timing across the boundary between the Speedcore instance and the surrounding host ASIC, along with how to perform full-chip simulation.

1.1 Download
Speedcore Clock and Reset Architecture User Guide (UG063)

This user guide details the clock structure for a Speedcore instance, covering the global core clock network, and interface clock networks. This guide also covers various clocking scenarios and their impact on timing closure.

1.6 Download