- Achronix and Mentor Partner to Provide Link Between High-Level Synthesis and FPGA Technology
- Achronix Speedcore eFPGAs fully supported by Catapult HLS
- Catapult HLS delivers integrated design and development environment to FPGA flow for 5G Wireless Applications
Santa Clara, Calif., August 7, 2018 –– Achronix Semiconductor Corporation, a leader in FPGA-based hardware accelerator devices and embedded FPGA (eFPGA) IP, today announced availability of an optimized high-level synthesis (HLS) flow from its partner, Mentor, a Siemens business, for its FPGA technology products.
As Achronix and Mentor partner, this integrated development environment enables designers to quickly go from C++ to FPGA using Mentor’s Catapult® HLS and Achronix’s ACE design tools. Initially used for 5G wireless applications to reduce the overall development effort and improve quality of results (QoR), it is suitable for any design targeting Achronix technology.
“The combination of Mentor’s powerful Catapult tools and Achronix’s embedded FPGA technology offer a truly unique value proposition for companies that require high performance FPGA technology in their SoC that can be configured using a proven C-based design flow,” remarks Steve Mensor, Achronix’s vice president of marketing. “This combined solution is a great testament of a close working relationship between the engineering groups at Mentor and Achronix. Our initial target was 5G wireless, but the unique capabilities of the overall solution will be valuable across many market segments that require the fastest development time.”
“We are happy to have Achronix and Mentor partner within our OpenDoor Program, and pleased to be an active member of the Achronix Partner Program. This open and collaborative partnership is very strategic and is already proving beneficial to our mutual customers,” notes Ellie Burns, director of marketing, Calypto Systems Division at Mentor. “Achronix eFPGA offers a tremendous ability to adapt to late changing and new requirements in a field programmable SoC. Coupled with Catapult HLS and the verification speed of C++, chip designers can now easily go from algorithm change to new low-power, high-performance hardware in days rather than weeks or months.”
The Catapult to Achronix Flow
The Catapult HLS to Speedcore embedded FPGA technology flow gives designers the ability to make algorithmic changes in late stages of IP development and to optimize the algorithm and the digital micro-architecture. The integrated verification environment allows reuse of the software tests for generated register transfer level (RTL) code, reducing the need for dedicated RTL test benches by more than 80%.
Achronix ACE design tools support Catapult’s RTL constructs and primitives. Currently Achronix libraries for its Speedcore eFPGA products and for its Speedster standalone FPGAs are integrated into the flow.
The Achronix high-performance and high-density FPGA technology can be used for diverse hardware acceleration applications in data center compute, networking and storage; 5G wireless infrastructure, network acceleration; advanced driver assistance systems (ADAS) and autonomous vehicles.
Early versions of the design and development environment are available now.