Achronix and Mentor Partner Linking High-Level Synthesis and FPGA Technology

Press Releases Date
  • Achronix and Mentor Partner to Provide Link Between High-Level Synthesis and FPGA Technology
  • Achronix Speedcore eFPGAs fully supported by Catapult HLS
  • Catapult HLS delivers integrated design and development environment to FPGA flow for 5G Wireless Applications

Santa Clara, Calif., August 7, 2018 –– Achronix Semiconductor Corporation, a leader in FPGA-based hardware accelerator devices and embedded FPGA (eFPGA) IP, today announced availability of an optimized high-level synthesis (HLS) flow from its partner, Mentor, a Siemens business, for its FPGA technology products.

As Achronix and Mentor partner, this integrated development environment enables designers to quickly go from C++ to FPGA using Mentor’s Catapult® HLS and Achronix’s ACE design tools. Initially used for 5G wireless applications to reduce the overall development effort and improve quality of results (QoR), it is suitable for any design targeting Achronix technology.

“The combination of Mentor’s powerful Catapult tools and Achronix’s embedded FPGA technology offer a truly unique value proposition for companies that require high performance FPGA technology in their SoC that can be configured using a proven C-based design flow,” remarks Steve Mensor, Achronix’s vice president of marketing. “This combined solution is a great testament of a close working relationship between the engineering groups at Mentor and Achronix. Our initial target was 5G wireless, but the unique capabilities of the overall solution will be valuable across many market segments that require the fastest development time.”

“We are happy to have Achronix and Mentor partner within our OpenDoor Program, and pleased to be an active member of the Achronix Partner Program. This open and collaborative partnership is very strategic and is already proving beneficial to our mutual customers,” notes Ellie Burns, director of marketing, Calypto Systems Division at Mentor. “Achronix eFPGA offers a tremendous ability to adapt to late changing and new requirements in a field programmable SoC. Coupled with Catapult HLS and the verification speed of C++, chip designers can now easily go from algorithm change to new low-power, high-performance hardware in days rather than weeks or months.”

The Catapult to Achronix Flow

The Catapult HLS to Speedcore embedded FPGA technology flow gives designers the ability to make algorithmic changes in late stages of IP development and to optimize the algorithm and the digital micro-architecture. The integrated verification environment allows reuse of the software tests for generated register transfer level (RTL) code, reducing the need for dedicated RTL test benches by more than 80%.

Achronix ACE design tools support Catapult’s RTL constructs and primitives. Currently Achronix libraries for its Speedcore eFPGA products and for its Speedster standalone FPGAs are integrated into the flow.

The Achronix high-performance and high-density FPGA technology can be used for diverse hardware acceleration applications in data center compute, networking and storage; 5G wireless infrastructure, network acceleration; advanced driver assistance systems (ADAS) and autonomous vehicles.

Availability

Early versions of the design and development environment are available now.

Forward-Looking Statements

This press release contains certain forward-looking statements within the meaning of the federal securities laws. These forward-looking statements generally are identified by the words “intend,” “future,” “may,” “will,” “would,” “will be,” and similar expressions. Forward-looking statements are predictions, projections and other statements about future events that are based on current expectations and assumptions and, as a result, are subject to risks and uncertainties. All statements, other than statements of present or historical fact included in this press release, including Achronix’s strategy, products, operations, prospects and pipeline expectations, and plans and objectives of management are forward-looking statements. Many factors could cause actual future events to differ materially from the forward-looking statements in this press release, including but not limited to: changes in domestic and foreign business, market, financial, political, and legal conditions and changes in the combined capital structure; the ability to implement business plans, forecasts, and other expectations and identify and realize additional opportunities; risks related to the rollout of Achronix’s business and the timing of expected business milestones; the effects of competition on Achronix’s business; the effects of the cyclical nature of the semiconductor industry on Achronix’s business; risks related to Achronix’s customer concentration; the risks to Achronix’s business if internal processes and information technology systems are not properly maintained; risks associated with Achronix’s operational dependence on independent contractors and third parties; risks associated with Achronix’s reliance on certain suppliers for, among other things, silicon wafers, and shortages or interruptions in supply of wafers and other supplies; risks and uncertainties related to Achronix’s international operations, including possible restrictions on cross-border investments which could harm Achronix’s financial position; and risks associated with Achronix’s ability to develop new products and adapt to new markets. The foregoing list of factors is not exhaustive. You should carefully consider the foregoing factors and the other risks and uncertainties described in the “Risk Factors” section of ACE’s registration statement on Form S-4, filed with the SEC on February 10, 2021, as may be amended from time to time, and other documents filed or that may be filed by ACE from time to time with the SEC and available on EDGAR at www.sec.gov. These filings identify and address other important risks and uncertainties that could cause actual events and results to differ materially from those contained in the forward-looking statements. There may be additional risks that Achronix does not presently know, or that Achronix currently believes are immaterial, that could also cause actual results to differ from those contained in the forward-looking statements. Forward-looking statements speak only as of the date they are made. Readers are cautioned not to put undue reliance on forward-looking statements as predictions of future events, and Achronix assumes no obligation and does not intend to update or revise these forward-looking statements, whether as a result of new information, future events, or otherwise, except as may be required by applicable law.

About Achronix Semiconductor Corporation

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-end FPGA-based data acceleration solutions, designed to address high-performance, compute-intensive and real-time processing applications. Achronix FPGA and eFPGA IP offerings are further enhanced by ready-to-use accelerator cards targeting AI, machine learning, networking and data center applications. All Achronix products are fully supported by a complete and optimized range of Achronix software tools called ACE, which enables customers to quickly develop their own custom applications.

Achronix has a global footprint, with sales and design teams across the U.S., Europe and Asia. In January 2021, Achronix entered into a definitive merger agreement with ACE Convergence Acquisition Corp. (Nasdaq: ACEV) in a transaction that would result in Achronix being listed on Nasdaq. The transaction is expected to close in the first half of 2021.

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Contacts

Bob Siller
Achronix Semiconductor Corporation
408-889-4142
bobsiller@achronix.com


Achronix and Speedster are registered trademarks, and Speedcore and Speedchip are trademarks of Achronix Semiconductor Corporation. All other brands, product names and marks are the property of their respective owners.