Unbeatable Bandwidth and Latency Performance

LOW POWER

Speedcore IP's combined static and dynamic power consumption is less than half that of high-performance standalone FPGAs.

HIGH PERFORMANCE

Speedcore eFPGA interfaces are massively parallel, single-ended buses with latency as low as 2ns. Whereas the latency performance for standalone FPGAs is typically 30ns to 100ns and is the performance bottleneck.

COST SAVINGS

Speedcore eFPGAs eliminate the standalone FPGA costs and reduces system production costs for the following items:

• Smaller PCB size
• Reduced PCB layer count
• Eliminate FPGA supporting components
• Improved system reliability

LOW RISK

Speedcore eFPGAs are based on the same technology used in Speedster22i FPGAs. ACE design tools support Speedster and Speedcore products. Customers can use ACE today to benchmark Speedcore performance, power and area utilization.

 

Speedcore Custom Blocks

Speedcore eFPGA IP has brought the power and flexibility of programmable logic to ASICs and SoCs. Customers can integrate a Speedcore eFPGA into an SoC for high-performance, compute-intensive and real-time processing applications such as AI, machine learning, 5G wireless, networking and automotive. Speedcore custom blocks greatly increase the capabilities of eFPGAs by allowing customers to define custom functions that can be added as additional blocks in the eFPGA fabric, alongside the traditional building blocks of LUTs, RAMs, and DSPs.

Speedcore custom blocks massively improve performance, power, and area, enabling functionality that has never before been possible in standalone FPGAs. With Speedcore custom blocks, customers gain ASIC efficiency while retaining FPGA flexibility, resulting in a highly efficient implementation that minimizes power and area while maximizing data throughput with ASIC-level performance.

SpeedcoreCustomBlockLayout

Custom Blocks Application Examples

Speedcore custom blocks can be defined collaboratively with Achronix through a detailed architecture analysis of acceleration workloads in the customer’s target application; for example:

  • A CNN-based object recognition algorithm. Conversion of this logic to use custom blocks reduced the area by over 40% by optimizing the DSP and memory blocks for matrix multiplication.
  • Large string search functions requiring parallel comparator arrays. Conversion to custom blocks resulted in area reduction of over 90%.
  • The core functionality of a 400 Gbps packet processing data-path running at 800 MHz implemented as Speedcore custom blocks with the programmable logic managing the analysis and control functionality. The resulting implementation supports the high throughput needed for packet processing applications — performance not possible in standalone FPGAs.

Design Tool Support

Achronix ACE design tools fully support Speedcore custom blocks from design capture to bitstream generation and system debug. Achronix creates a unique GUI for each Speedcore custom block that manages all configuration rules. ACE contains the full timing details for all configurations of the Speedcore custom block, which allows ACE to complete timing-driven place-and-route for designs. Customers can use the powerful floorplanner tool for design optimization and to make regional or site assignments for all block instances. ACE also includes a critical path analysis tool to analyze timing. Customers also have access to ACE’s powerful Snapshot embedded logic analyzer to create complex triggers and show run-time signals within a Speedcore instance.

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Industry-standard, proven design tools

The Achronix CAD Environment (ACE) design tools are powerful and easy to use. ACE includes an Achronix version of Synplify-Pro from Synopsys for best-in-class synthesis and outputs simulation libraries that work with ModelSim from Mentor Graphics, VCS from Synopsys, IES from Cadence and Riviera-PRO from Aldec.

ACE design tools deliver the industry’s highest quality-of-results for performance, area and compile times. Additionally, ACE includes an example Speedcore instance that you can use to benchmark performance and power consumption against your current solutions.

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We are here to help and support your existing engineering teams.

Achronix’s excellent support personnel and detailed documentation allows you to quickly onboard your team and jumpstart your project. We also offer one-day, on-site workshops in multicore CPU acceleration for server applications, ASIC integration flow or Achronix eFPGA programming software benchmarks.

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Our experts are happy to advise you on how Achronix can help with your toughest design challenges.