Production–proven tools that integrate with common EDA flows.
ACE works in conjunction with industry-standard synthesis tools, allowing FPGA designers to easily map their designs into Achronix Speedster®22i FPGAs.
ACE includes an Achronix-optimized version of Synplify-Pro from Synopsys. Achronix simulation libraries are supported by ModelSim from Mentor Graphics, VCS from Synopsys and Riviera-PRO from Aldec.
Standard RTL (VHDL and Verilog) input together with industry-standard simulation ensures that the Achronix design flow is straightforward for existing FPGA designers.