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  • Configuring Your Speedcore eFPGA, Part 2: Configuration Time July 30, 2018 by Volkan Oktem

    As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to program a bitstream into a Speedcore eFPGA depends on the configuration mode being used, the data width, clock frequency, and of course, the size of the configuration bitstream. Configuration of the Speedcore eFPGA consists of the following steps: Clearing the Speedcore eFPGA’s configuration memory Configuration bitstream programming Additional control state transitions to sequence resets and to switch the eFPGA …

    Configuring your Speedcore eFPGA, Part 1: Configuration Interfaces July 16, 2018 by Volkan Oktem

    Each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store the eFPGA’s configuration bits. Each Speedcore instance contains its own FPGA configuration unit (FCU) that initializes, configures, and manages the Speedcore eFPGA’s core logic array. For example, if you instantiate three Speedcore eFPGAs in your ASIC/SoC design, there will be three FCUs on the chip. Each FCU has a set of configuration pins and a set of configuration-mode pins that help to determine how the configuration pins will operate. The figure below shows the relationship …

    How Big Should your eFPGA be? Here are Some Hints. June 29, 2018 by Volkan Oktem

    Once you’ve made the correct decision to add Speedcore eFPGA IP to your ASIC or SoC design, the next question you’ll need to answer is how large to make the eFPGA. That’s a multi-dimensional question because Speedcore eFPGAs contain many types of blocks including: LUTs – grouped together in reconfigurable logic blocks (RLBs) along with MUXes, registers, and 4-bit ALUs BRAMs – dual-ported, 20Kb block RAMs LRAMs – single-ported, 4Kb logic RAMs DSP64 math units You’ll need to decide how many of each type of block you’ll need to implement your application(s) within your overall ASIC or SoC design. Once you make those decisions, Achronix …

    When, Why, and How Should You Use Embedded FPGA Technology for Hardware Acceleration? June 7, 2018 by Alok Sanghavi

    If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn’t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors — then progressing to gates, ALUs, microprocessors, and memories. FPGAs are simply one more useful component in the tool box, available for decades as standalone products, and now available for integration into your IC design using Achronix’s Speedcore eFPGA, supported by Achronix’s ACE design tools. These products allow you to easily incorporate the performance and flexibility of programmable logic into your next ASIC or FPGA design. The questions then …

    My Path to Achronix Applications Engineering April 26, 2018 by Katie Purcell

    Growing up in Virginia, I never thought I would become an engineer. Not that I didn’t want to be an engineer — the thought just never crossed my mind. As a kid, I spent most of my free time pursuing various arts. I loved music, learning to play the flute, piccolo, and later the electric bass, on top of spending many years studying classical ballet. And it may not be considered art, but I also loved baking; the process of perfecting old recipes and the creativity of coming up with new ones. A Common Thread The common thread with all of these creative endeavors is …