Blog Posts

Archives:
  • 2017
  • Check out our Recent Video on the Basics of eFPGA Acceleration September 29, 2017 by Alok Sanghavi

    Our existing customers ask us some pretty big questions: “How can this technology implement a step-change in my specific process? How can Speedcore IP be integrated in my SoC? How can you increase the performance of my ASIC?” We revel in answering such questions. However, when we first meet with a company interested in our embedded FPGA (eFPGA) IP, often the question is very simply, “At the most basic level, what can it do for me?” This question may be the most important one we’ll ever answer for them. A few months ago Achronix’s systems architect Kent Orthner made a short video with Ed Sperling, …

    The Big Trend at Hot Chips This Year? Hybrid Architectures Incorporating FPGA Fabrics for AI and Machine Learning Applications September 1, 2017 by Randy Fish

    Achronix was delighted to attend the Hot Chips event in Cupertino once again this August. This year saw a bumper turnout, with some very fascinating speakers providing some great insights into the industry. The Achronix team had a chance to meet with many talented people in the industry, swap the usual industry gossip, and pick up several highly promising new business leads. One very noticeable trend at this year’s conference was the emphasis placed on development of hybrid architectures incorporating FPGA fabrics in order to deliver ASIC-like data center acceleration. Firstly, Microsoft announced Project Brainwave, an acceleration platform for deep learning and AI applications. This …

    Closing Timing with Speedcore eFPGAs Made Easy August 3, 2017 by Volkan Oktem

    Speedcore eFPGAs are embeddable IP that include look-up tables, memories, and DSP building blocks, allowing designers to add a programmable logic fabric to their SoC. The Speedcore IP can be configured to any size as dictated by the end application. The SoC supplier defines the number of LUTs, memory resources, and DSP64 blocks for their Speedcore instance. A short time later, Achronix delivers the IP as a GDS plus supporting libraries, models and documentation. Once this custom Speedcore block is embedded in the SoC, the end user can use the Achronix CAD Environment (ACE) design tools which are traditional FPGA design tools and workflows to …

    Achronix FPGAs and NIC-based Data Center Acceleration August 1, 2017 by Steve Mensor

    The data center market, as many would observe, is now a major commercial sweet spot for the tech sector, with positive revenue growth; a hotbed for innovation. But the industry has a number of hurdles. Data centers now have to deal with oceans of unstructured data. Over the years data centers have moved away from custom to commodity hardware in order to maintain scalability, redundancy and low costs, while achieving appropriately high port counts, low power consumption and high performance. Flexibility is critical because every task is different. The widespread adoption of Intel’s x86 Xeon CPUs was a step in the right direction. These have …

    Who’s Who in the Zoo June 28, 2017 by Steve Mensor

    While the concept of eFPGA IP is fairly straightforward, the number of parties involved and their responsibilities may not be clear at the outset. It is the very programmable nature of an eFPGA that can cause confusion of who is responsible for what. With a standalone FPGA, there are three parties involved: the FPGA vendor, the foundry and the end user. The relationships between each are straightforward and well understood. Communication happens between the FPGA vendor and its foundry, but not between the end user and the foundry. The FPGA vendor communicates directly with the end user, delivering design tools and silicon. With an eFPGA, …