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  • Achronix’s Next-Generation, 7nm FPGA Family Will Feature Micron’s Blazingly Fast GDDR6 Memory – To 4 Tbps and Beyond November 12, 2018 by Manoj Roge

    Micron Technology announced today that its high-performance GDDR6 SDRAM (in volume production since June) will be the high-speed memory of choice for Achronix’s yet-to-be-announced, next-generation FPGA family,  making Achronix the world’s first FPGA vendor with announced GDDR6 support. Achronix has worked closely with Micron on GDDR6 compatibility and this announcement of Achronix’s next-generation FPGA family support is proof of this extremely close partnership. Next-generation Achronix FPGAs will be fabricated on TSMC’s industry-leading 7nm process node. Achronix’s next-generation FPGAs will fully exploit the GDDR6 SDRAM’s extreme memory bandwidth because they will incorporate as many as eight hard GDDR6 memory interfaces — each with as many as …

    Speedcore eFPGAs are an Enabling Technology for 360° Surround-view Systems November 12, 2018 by Alok Sanghavi

    Next-generation video applications such as surveillance, object detection, motion analysis now rely on 360° embedded vision. In these systems, multiple real-time camera streams (up to six) are processed together frame by frame, with each frame corrected for distortion and other image artifacts, adjusted for exposure and white balance, and then stitched together dynamically into a single 360° panoramic view, then output at 4K 60 fps and ultimately projected on a spherical coordinate space. Today’s high-resolution fish-eye cameras lenses used in such applications typically have a wide-angle field of view (FOV). One of the biggest bottlenecks in surround-view camera systems is storing and accessing multiple-camera input …

    Learning to Share – Embedded FPGA Timing Closure October 2, 2018 by Alok Sanghavi

    When we start school as young children, one of the first lessons we learn is how to share (followed quickly by not running with scissors). As our Sr. Director of Systems Engineering, Kent Orthner, discussed at DAC this past June, sharing is also key when it comes to closing timing with embedded FPGAs (eFPGAs). With an eFPGA such as Speedcore IP, the task of closing timing is owned by two people: the ASIC designer, responsible for the design in the host ASIC, and the FPGA designer, responsible for the design targeting the FPGA. This situation is very analogous to how timing is closed on a …

    Configuring Your Speedcore eFPGA, Part 2: Configuration Time July 30, 2018 by Volkan Oktem

    As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to program a bitstream into a Speedcore eFPGA depends on the configuration mode being used, the data width, clock frequency, and of course, the size of the configuration bitstream. Configuration of the Speedcore eFPGA consists of the following steps: Clearing the Speedcore eFPGA’s configuration memory Configuration bitstream programming Additional control state transitions to sequence resets and to switch the eFPGA …

    Configuring your Speedcore eFPGA, Part 1: Configuration Interfaces July 16, 2018 by Volkan Oktem

    Each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store the eFPGA’s configuration bits. Each Speedcore instance contains its own FPGA configuration unit (FCU) that initializes, configures, and manages the Speedcore eFPGA’s core logic array. For example, if you instantiate three Speedcore eFPGAs in your ASIC/SoC design, there will be three FCUs on the chip. Each FCU has a set of configuration pins and a set of configuration-mode pins that help to determine how the configuration pins will operate. The figure below shows the relationship …