Documentation

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Title Description Version Released Date Document File
FPGAs Enable the Next Generation of Communication and Networking Solutions (WP021)

Communications and networking systems that extend from the edges of the 5G network to the switches inside data centers are placing extreme pressure on the ability of silicon to support the computational and data-transfer rates they require. Traditionally programmable logic provided the best mixture of flexibility and speed for these systems, but has been challenged in recent years by the increase in speed. Through the inclusion of an innovative, multilevel network on chip that allows data to be streamed easily around the device without impacting the FPGA fabric, the Speedster7t architecture ensures all device resources are used to their full potential.

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FPGAs and eFPGAs Accelerate ML Inference at the Edge (WP026)

With the rapid proliferation of Internet-of-Things (IoT) and billions of connected devices, there is a paradigm shift taking place where big data is not only being processed in the core data center but also at the network edge. Field Programmable Gate Arrays (FPGAs), sitting at the intersection of performance and flexibility, are a promising solution for deep learning edge inference applications.

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Evaluating Speedcore IP For Your ASIC (WP007)

Phase zero is the beginning of a Speedcore design and how you begin matters. From a technical perspective, you will want to explore the possibilities to maximize the benefit of having your ASIC deployed with a Speedcore instance with a mix of resources well suited to your current and future programmed configurations. Achronix will help you along this road, providing support, training and feedback in employing tools, benchmarking designs and dealing with optimization issues.

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Enhancing eFPGA Functionality with Speedcore Custom Blocks (WP009)

Achronix Speedcore™ eFPGA IP can be integrated in an SoC for high-performance, compute-intensive and realtime processing applications such as AI, automotive sensor fusion, network acceleration and wireless 5G. Speedcore eFPGA IP is a game-changer for SoC developers, allowing them to add flexibility to their products by including FPGA technology in their ASICs. For SoC development, companies specify the quantity and mix of lookup-table (LUT) logic, embedded memory blocks, and DSP blocks that best meets their needs. Along with these functions, Achronix now offers the ability for companies to define custom block functions, optimized for their application, that can also be included in the eFPGA fabric. Speedcore custom blocks increase die area efficiency, increase performance and lower power.

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Enabling the Next Generation of 5G Platforms (WP029)

Radio access networks (RANs) and associated core network hierarchy, which link end-user equipment to both the central telecom network and the cloud, are essential in building ubiquitous cellular connectivity to expand the number and breadth of use cases that can be supported by the technology. This paper outlines the current status of 5G standards and rollout, summarizes the new use cases 5G RANs need to support and examines the standards evolution to support higher bandwidth and additional use cases. Finally, it also explains how Achronix FPGA technology can be utilized by developers to meet the fundamental challenge facing them.

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Title Description Version Released Date Document File
Measuring Accurate Toggle Rates

When calculating dynamic power for a design, one input to any power estimation is the toggle rate of the signals. In most circumstances, the value used will be one of the industry standards of either 12.5% or 25% — values derived from a wide range of designs.

 1.0 Measuring_Accurate_Toggle_Rates_AN010.pdf
Formal Verification in the ACE Flow (AN013)

This application note covers the formal verification support available in the ACE environment. ACE currently is capable of supporting formal equivalency checking in its design flow, enabling the user to verify the synthesized netlist against the output at the different stages in the ACE flow.

 1.0 Formal_Verification_in_the_ACE_Flow_AN013.pdf
Device Binning Methodologies (AN005)

The manufacturing process for any silicon device inevitably has variations, whether those are in the thickness of a substrate or track, the purity of a conductor, position of the die on the wafer, or one of a myriad of many other physical effects.

 1.0 Device_Binning_Methodologies_AN005.pdf
Coding Guidelines for Speedcore eFPGAs (AN003)

This application note details certain specific design elements that, with certain coding constructs and constraints, can improve timing performance or lower resource utilization.

 2.1 Coding_Guidelines_for_Speedcore_eFPGAs_AN003.pdf
Clock Design Planning for Speedcore eFPGAs (AN011)

Speedcore eFPGAs have a robust clocking architecture. While some designs only use a single main clock, others can have complicated clocking schemes. It is important for designers to understand the different types of clocks available in the Speedcore architecture, and how to get the best design out of the clocking resources available.

 1.0 Clock_Design_Planning_for_Speedcore_eFPGAs_AN011.pdf
Title Description Version Released Date Document File
Speedster7t DDR User Guide (UG096)

The Achronix Speedster7t FPGA family provides DDR subsystems that enable the user to fully utilize the low latency and high-bandwidth efficiency of these interfaces for critical applications such as high-performance compute and machine learning systems. The DDR subsystem supports memory devices and features compliant with JEDEC Standard JESD79-4B.

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Speedster7t Configuration User Guide (UG094)

At startup, Speedster7t FPGAs require configuration via a bitstream. This user guide details the programming process through one of four available interfaces in the FPGA configuration unit (FCU), the logic controlling the configuration process.

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Speedster7t Component Library User Guide (UG086)

The Achronix Speedster7t component library provides the user with building blocks that may be instantiated into the user’s design. These components provide access to low-level fabric primitives, complex I/O blocks, and higher level design components. Each library element entry describes the operation of the component as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design.

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Speedster7t Clock and Reset Architecture User Guide (UG083)

This document explains the architecture of the different clock networks in a Speedster7t FPGA and and provides information on how to use the clocks.

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Speedster7t AC7t1500 Board Designers Guide (UG101)

The Speedster7t AC7t1500 FPGA includes several advanced interfaces that require careful design in order to operate at their peak performance. This guide is intended as a general overview of PCB design principles that help the designer get the most out of the AC7t1500 FPGA. This guide is broken down by system components. These include the Ethernet, the PCIe5, the GDDR6 memory and the DDR4 memory interfaces.

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