Documentation

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Title Description Version Released Date Document File
How to Meet Power Performance and Cost for Autonomous Vehicle Systems using Speedcore eFPGAs (WP015)

In the advanced, fully autonomous, self-driving vehicles of the future, the existence of dozens and even hundreds of distributed CPUs and numerous other processing elements is assured. Peripheral sensor-fusion and other processing tasks can be served by ASICs, SoCs, or traditional FPGAs. But the introduction of embedded FPGA blocks such as Achronix's Speedcore eFPGA IP provides numerous system-design advantages in terms of shorter latency, more security, greater bandwidth, and better reliability that are simply not possible when using CPUs, GPUs, or even standalone FPGAs.

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Achieving ASIC Timing Closure with Speedcore eFPGAs (WP013)

Achronix's Speedcore eFPGA IP allows companies to embed a programmable logic fabric in their ASICs, delivering to end users the capability to modify or upgrade the functionality of an ASIC after being deployed in the field. This flexibility dramatically expands the solution space that can be served by the ASIC as it can be updated to support changing standards and algorithms. Timing closure is particularly challenging due to the fact that the eFPGA fabric may host any number of designs over the course of device operation. Each of those designs must work independently with the rest of the ASIC, and timing closure can only be said to have been met if all of the possible designs targeting the eFPGA fabric can meet timing.

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2018 Ushers in a Renewed Push to the Edge (WP012)

The past decade has seen massive growth in centralized computing, with data processing flowing to the cloud to take advantage of low-cost dedicated data centers. It was a trend that seemed at odds with the general trend in computing — a trend that started with the mainframe but moved progressively towards ambient intelligence and the internet of things (IoT). As we move into 2018, this centralization is reaching its limit. The volume of data that will be needed to drive the next wave of applications is beginning to force a change in direction.

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The Ideal Solution for AI Applications — Speedcore eFPGAs (WP011)

AI requires a careful balance of datapath performance, memory latency, and throughput that requires an approach based on pulling as much of the functionality as possible into an ASIC or SoC. But that single-chip device needs plasticity to be able to handle the changes in structure that are inevitable in machine-learning projects. Adding eFPGA technology provides the mixture of flexibility and support for custom logic that the market requires. Achronix provides not only the building blocks required for an AI-ready eFPGA solution, but also delivers a framework that supports design through to debug and test of the final application. Only Achronix Speedcore IP has the right mix of features for advanced AI that will support a new generation of real-time, self-learning systems.

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Enhancing eFPGA Functionality with Speedcore Custom Blocks (WP009)

Achronix Speedcore™ eFPGA IP can be integrated in an SoC for high-performance, compute-intensive and realtime processing applications such as AI, automotive sensor fusion, network acceleration and wireless 5G. Speedcore eFPGA IP is a game-changer for SoC developers, allowing them to add flexibility to their products by including FPGA technology in their ASICs. For SoC development, companies specify the quantity and mix of lookup-table (LUT) logic, embedded memory blocks, and DSP blocks that best meets their needs. Along with these functions, Achronix now offers the ability for companies to define custom block functions, optimized for their application, that can also be included in the eFPGA fabric. Speedcore custom blocks increase die area efficiency, increase performance and lower power.

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Title Description Version Released Date Document File
Measuring Accurate Toggle Rates

When calculating dynamic power for a design, one input to any power estimation is the toggle rate of the signals. In most circumstances, the value used will be one of the industry standards of either 12.5% or 25% — values derived from a wide range of designs.

1.0 Measuring_Accurate_Toggle_Rates_AN010.pdf
Formal Verification in the ACE Flow (AN013)

This application note covers the formal verification support available in the ACE environment. ACE currently is capable of supporting formal equivalency checking in its design flow, enabling the user to verify the synthesized netlist against the output at the different stages in the ACE flow.

1.0 Formal_Verification_in_the_ACE_Flow_AN013.pdf
Clock Design Planning for Speedcore eFPGAs (AN011)

Speedcore eFPGAs have a robust clocking architecture. While some designs only use a single main clock, others can have complicated clocking schemes. It is important for designers to understand the different types of clocks available in the Speedcore architecture, and how to get the best design out of the clocking resources available.

1.0 Clock_Design_Planning_for_Speedcore_eFPGAs_AN011.pdf
Device Binning Methodologies (AN005)

The manufacturing process for any silicon device inevitably has variations, whether those are in the thickness of a substrate or track, the purity of a conductor, position of the die on the wafer, or one of a myriad of many other physical effects.

1.0 Device_Binning_Methodologies_AN005.pdf
Title Description Version Released Date Document File
Speedcore Power Estimator User Guide (UG073)

The Achronix Speedcore Power Estimator tool provides a platform to calculate the power requirements for Achronix Speedcore eFPGAs. This user guide gives a detailed overview of the thermal and power needs depending on the device, environment and utilization of components in the design.

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Speedcore Configuration User Guide (UG061)

During normal SoC operation, the Speedcore eFPGA core requires configuration by the end user. This guide covers the details of how to configure a Speedcore instance via JTAG, CPU, or serial flash interface. Also included are details on the Achronix Configuration Bus (ACB) interface that can be used to program configuration bits for ASIC IP surrounding the Speedcore eFPGA.

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Speedcore Software Integration and Flow User Guide (UG062)

Speedcore Software Integration and Flow User Guide (UG062)

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Speedcore Clock and Reset Architecture User Guide (UG063)

This user guide details the clock structure for a Speedcore instance, covering the global core clock network, and interface clock networks. This guide also covers various clocking scenarios and their impact on timing closure.

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Speedster7t Network on Chip User Guide (UG089)

The Speedster7t FPGA family of devices has a network hierarchy that enables extremely high-speed dataflow between the FPGA core and the interfaces around the periphery, as well as between logic within the FPGA itself. This on-chip network hierarchy supports a cross-sectional bidirectional bandwidth of 20 Tbps. It supports a multitude of interface protocols including GDDR6, DDR4/5, 400G Ethernet, and PCI Express Gen5 data streams, while greatly simplifying access to memory and high-speed protocols. Achronix's network on chip (NoC) provides for read/write transactions throughout the device, as well as specialized support for 400G Ethernet streams in selected columns. The features of the NoC described in this user guide generally pertain to the entire Speedster7t family of devices. In order to help users understand specific connections and features of the NoC, this user guide focuses on the NoC as implemented in the AC7t1500 device.

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