Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
Measuring Accurate Toggle Rates

When calculating dynamic power for a design, one input to any power estimation is the toggle rate of the signals. In most circumstances, the value used will be one of the industry standards of either 12.5% or 25% — values derived from a wide range of designs.

1.00 Measuring_Accurate_Toggle_Rates_AN010.pdf
Formal Verification in the ACE Flow

This application note covers the formal verification support available in the ACE environment. ACE currently is capable of supporting formal equivalency checking in its design flow, enabling the user to verify the synthesized netlist against the output at the different stages in the ACE flow.

1.00 Formal_Verification_in_the_ACE_Flow_AN013.pdf
Title Description Version Released Date Document File
Speedster7t Clock and Reset Architecture User Guide (UG083)

Achronix’s new 7nm Speedster 7t FPGA family is specifically designed to deliver extremely high performance for ® demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center. In order to meet the demand of high performance and complex designs, the clock network for Speedster7t FPGAs has been designed with numerous high performance clocks that allow for maximum routability. This document explains the architecture of the different clock networks in a Speedster7t FPGA, as well as information on how to use the clocks. It is intended to help designers understand and choose the best clocking options for their design on a Speedster7t FPGA.

1.00 Download
Speedcore Power Estimator User Guide (UG073)

The Achronix Speedcore Power Estimator tool provides a platform to calculate the power requirements for Achronix Speedcore eFPGAs. This user guide gives a detailed overview of the thermal and power needs depending on the device, environment and utilization of components in the design.

1.40 Download
Speedcore IP Component Library User Guide (UG065)

The Achronix Speedster16t macro cell library provides the user with building blocks that may be instantiated into the user’s design. In this guide, each library element entry describes the operation of the macro as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design.

1.10 Download
Bitstream Programming and Debug Interface User Guide (UG004)

The embedded programming and configuration logic in the Achronix core is designed to support a variety of programming and debugging options.This guide details those options and how to implement them at the board level, including using the Achronix STAPL player.

1.60 Download
Speedster22i DDR3 User Guide (UG031)

Speedster22i DDR3 User Guide (UG031)

3.00 Download