Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

Select the individual tabs below to browse through each type of documentation. Or use the filter to only see documentation related to your product of interest.

Some documents are restricted (denoted by the lock symbol in the download button) and require a support portal account to access the download. To download a restricted document, enter your support portal account credentials when prompted. Don't have a support portal account? Register for an account here: Achronix Support Account Registration

Title Description Version Released Date Document File
Formal Verification in the ACE Flow (AN013)

This application note covers the formal verification support available in the ACE environment. ACE currently is capable of supporting formal equivalency checking in its design flow, enabling the user to verify the synthesized netlist against the output at the different stages in the ACE flow.

1.0 Formal_Verification_in_the_ACE_Flow_AN013.pdf
Device Binning Methodologies (AN005)

The manufacturing process for any silicon device inevitably has variations, whether those are in the thickness of a substrate or track, the purity of a conductor, position of the die on the wafer, or one of a myriad of many other physical effects.

1.0 Device_Binning_Methodologies_AN005.pdf
Title Description Version Released Date Document File
Speedcore Configuration User Guide (UG061)

During normal SoC operation, the Speedcore eFPGA core requires configuration by the end user. This guide covers the details of how to configure a Speedcore instance via JTAG, CPU, or serial flash interface. Also included are details on the Achronix Configuration Bus (ACB) interface that can be used to program configuration bits for ASIC IP surrounding the Speedcore eFPGA.

2.9 Download
Synthesis User Guide (UG018)

This user guide describes how to use Synplify Pro from Synopsys to synthesize a design and generate a netlist for implementation in Achronix devices. Suggested optimization techniques are also included.

1.4 Download
Speedcore Power Estimator User Guide (UG073)

The Achronix Speedcore Power Estimator tool provides a platform to calculate the power requirements for Achronix Speedcore eFPGAs. This user guide gives a detailed overview of the thermal and power needs depending on the device, environment and utilization of components in the design.

1.4 Download
Speedcore IP Component Library User Guide (UG065)

The Achronix Speedster16t macro cell library provides the user with building blocks that may be instantiated into the user’s design. In this guide, each library element entry describes the operation of the macro as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design.

1.16 Download
Bitstream Programming and Debug Interface User Guide (UG004)

The embedded programming and configuration logic in the Achronix core is designed to support a variety of programming and debugging options.This guide details those options and how to implement them at the board level, including using the Achronix STAPL player.

1.6 Download