Supercharge your SoC with Achronix’s silicon-proven Speedcore™ eFPGA technology.
Speedcore embedded FPGA (eFPGA) IP has brought the performance and flexibility of programmable logic to ASICs and SoCs. Customers can integrate a Speedcore eFPGA IP into an ASIC or SoC for high-performance, compute-intensive and real-time processing applications such as artificial intelligence (AI), machine learning (ML), 5G wireless, networking, storage and automotive.
What is an eFPGA?
An embedded FPGA (eFPGA) is an IP core that is embedded within a custom ASIC or SoC. The IP can be licensed for use similar to that of other IP used in semiconductor designs. Unlike a standalone FPGA, eFPGA IP designers can select the exact amount of logic, DSP (or MLP) and memory resources required for their application. An eFPGA instance can also be used when flexibility is needed while lowering system cost, power and board space by eliminating the excess features of the standalone FPGA which are not required when moving into high-volume production.
Achronix is the only high-end FPGA supplier who provides both discrete FPGAs as well as eFPGA IP proven in production applications.
Benefits of Speedcore eFPGA IP
Designing for Speedcore eFPGA IP
Once a Speedcore eFPGA has been designed into your ASIC, it can be programmed using the Achronix Tool Suite with a flow identical to that of a standalone FPGA. Achronix creates a target eFPGA instance that includes the customer's specific eFPGA IP implementation in the Achronix Tool Suite. The Achronix Tool Suite allows for RTL synthesis, place and route, timing analysis and programming the eFPGA IP just like a standalone FPGA.
Achieving ASIC Timing Closure with Speedcore eFPGAs (WP013)
Achronix's Speedcore eFPGA IP allows companies to embed a programmable logic fabric in their ASICs, delivering to end users the capability to modify or upgrade the functionality of an ASIC after being deployed in the field. This flexibility dramatically expands the solution space that can be served by the ASIC as it can be updated to support changing standards and algorithms. Timing closure is particularly challenging due to the fact that the eFPGA fabric may host any number of designs over the course of device operation. Each of those designs must work independently with the rest of the ASIC, and timing closure can only be said to have been met if all of the possible designs targeting the eFPGA fabric can meet timing.
EFPGA Acceleration in SoCs — Understanding the Speedcore IP Design Process (WP008)
The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedded in an ASIC, are available to an ASIC development team either as products of the ACE design tools or as deliverables provided by Achronix. This methodology has already been proven in silicon and readily accommodates variations and preferences in company-specific ASIC development methodologies.
Embedded FPGA – a New System-Level Programming Paradigm (WP006)
The current public debate on the future of the semiconductor industry has turned to discussions about a growing selection of technologies that focuses instead on new system architectures and better use of available silicon through new concepts in circuit, device, and packaging design. The emergence of embedded FPGA is, in fact, not only essential at this juncture of the microelectronics history, but also inevitable. To understand this, a review of the history of FPGA technology is in order.
Enhancing eFPGA Functionality with Speedcore Custom Blocks (WP009)
Achronix Speedcore™ eFPGA IP can be integrated in an SoC for high-performance, compute-intensive and realtime processing applications such as AI, automotive sensor fusion, network acceleration and wireless 5G. Speedcore eFPGA IP is a game-changer for SoC developers, allowing them to add flexibility to their products by including FPGA technology in their ASICs. For SoC development, companies specify the quantity and mix of lookup-table (LUT) logic, embedded memory blocks, and DSP blocks that best meets their needs. Along with these functions, Achronix now offers the ability for companies to define custom block functions, optimized for their application, that can also be included in the eFPGA fabric. Speedcore custom blocks increase die area efficiency, increase performance and lower power.
Phase zero is the beginning of a Speedcore design and how you begin matters. From a technical perspective, you will want to explore the possibilities to maximize the benefit of having your ASIC deployed with a Speedcore instance with a mix of resources well suited to your current and future programmed configurations. Achronix will help you along this road, providing support, training and feedback in employing tools, benchmarking designs and dealing with optimization issues.
How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity (WP017)
Intelligent server adapters, or SmartNICs, boost server performance in cloud and private data centers by offloading network processing workloads and tasks from server CPUs. Offloading network processing to a SmartNIC is not a new concept — for example, there are NICs that offload some network-processing functions such as checksum computation and segmentation. However, the rapid explosion in data-center network traffic driven by software-defined networking (SDN), Open vSwitch (OVS), and network functions virtualization (NFV) demands a new class of NIC with even greater offload capabilities: the SmartNIC.
How to Meet Power Performance and Cost for Autonomous Vehicle Systems using Speedcore eFPGAs (WP015)
In the advanced, fully autonomous, self-driving vehicles of the future, the existence of dozens and even hundreds of distributed CPUs and numerous other processing elements is assured. Peripheral sensor-fusion and other processing tasks can be served by ASICs, SoCs, or traditional FPGAs. But the introduction of embedded FPGA blocks such as Achronix's Speedcore eFPGA IP provides numerous system-design advantages in terms of shorter latency, more security, greater bandwidth, and better reliability that are simply not possible when using CPUs, GPUs, or even standalone FPGAs.
Mine Cryptocurrencies Sooner, Faster, and Cheaper with Achronix Speedcore Embedded FPGAs (WP014)
New cryptocurrencies such as Monero introduce ASIC-resistance and memory-hardness to prevent ASICs from being built that give some operators a competitive mining advantage over others who do not have access to the same technology. This white paper discusses the relevant background and presents a solution based on Achronix Speedcore™ embedded FPGAs (eFPGAs), enabling users to regain a highly profitable advantage over competing solutions.
The Achronix Speedster16t macro cell library provides the user with building blocks that may be instantiated into the user’s design. In this guide, each library element entry describes the operation of the macro as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design.
Speedcore IP is embedded FPGA (eFPGA) that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements.
The Ideal Solution for AI Applications — Speedcore eFPGAs (WP011)
AI requires a careful balance of datapath performance, memory latency, and throughput that requires an approach based on pulling as much of the functionality as possible into an ASIC or SoC. But that single-chip device needs plasticity to be able to handle the changes in structure that are inevitable in machine-learning projects. Adding eFPGA technology provides the mixture of flexibility and support for custom logic that the market requires. Achronix provides not only the building blocks required for an AI-ready eFPGA solution, but also delivers a framework that supports design through to debug and test of the final application. Only Achronix Speedcore IP has the right mix of features for advanced AI that will support a new generation of real-time, self-learning systems.
Embedded FPGAs (eFPGAs) bring the power and flexibility of programmable logic to ASICs and SoCs. With eFPGAs, machine learning (ML) can be integrated in new form-factors such as mobile edge compute, IoT aggregation and SmartNIC.
In this webinar you will learn how to maximize hardware assurance (HwA) for critical IP in the semiconductor manufacturing process using eFPGA technology. Hardware assurance is of critical importance for manufacturing semiconductors in applications with heightened security requirements. See how eFPGAs can help to reduce the risk of critical IP getting compromised during the entire life cycle of the ASIC.
In the quest to accelerate and optimize today’s computing challenges such as AI inference, our system designs have to be flexible above all else. At the confluence of speed and flexibility are today’s new FPGAs and e-FPGA IP. In this episode of Chalk Talk, Amelia Dalton chats with former Achronix Sr. Director of Strategy and Planning about how to design systems to be both fast and future-proof using FPGA and e-FPGA technology.
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