- Steve Mensor to present “Embedded FPGA (eFPGA) for Processor and Algorithm Acceleration” at SEE/MAPLD
- Will highlight technology’s application for 5G wireless, HPC, ADAS and autonomous vehicles, machine learning and computer vision
Santa Clara, Calif., May 15, 2018 –– Achronix Semiconductor Corporation, a leader in field programmable gate array (FPGA)-based hardware accelerator devices and embedded FPGA (eFPGA) intellectual property (IP), will demonstrate the versatility of its Speedcore™ eFPGA devices next week at SEE/MAPLD and Embedded Vision Summit.
Steve Mensor, Achronix’s vice president of marketing, will present “Embedded FPGA (eFPGA) for Processor and Algorithm Acceleration” Wednesday, May 23, at 11:10 a.m. during the Single Event Effects Symposium/Military and Aerospace Programmable Logic Devices (SEE/MAPLD) Workshop.
Achronix’s booth at both conferences will highlight its eFPGA technology for 5G wireless, high–performance computing (HPC), advanced driver assistance systems (ADAS) and autonomous vehicles, machine learning and computer vision applications.
SEEM/MAPLD’s exhibition will run during meal and coffee breaks between technical sessions Tuesday, May 22, from 9:30 a.m. to 8 p.m. and Wednesday, May 23, from 9:30 a.m. until 1 p.m. at the Marriott La Jolla in San Diego, Calif.
The Embedded Vision Summit Showcase will be open Tuesday from noon until 8 p.m. with a reception from 6 p.m. to 8 p.m. Wednesday hours are 10:30 p.m. until 6 p.m. It will be held at the Santa Clara Convention Center in Santa Clara.
For more information about Achronix, go to: www.achronix.com/events.
About Speedcore eFPGA
Speedcore eFPGA IP can be integrated into an ASIC or SoC to provide a customized programmable fabric. Users specify their logic, memory and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements. Speedcore look-up-tables (LUTs), RAM blocks and DSP64 blocks can be assembled like building blocks to create the optimal programmable fabric for any given application.