New IP delivers up to 32 Gbps per lane, deterministic latency, and scalable connectivity for next-generation waveband converter systems.
Santa Clara, Calif., August 26, 2026 – Achronix Semiconductor Corporation, the leader in data acceleration FPGAs, announced the availability of its high-performance JESD204C IP core for the Speedster®7t FPGA family. Designed to connect advanced analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) to programmable logic, each core supports data rates of up to 32 Gbps per lane and up to eight lanes per link, delivering an aggregate serial line rate of up to 256 Gbps, while combining up to four cores enables aggregate performance of up to 1 Tbps. This standards-based core enables Speedster7t FPGAs to seamlessly interface with very high-speed JESD204B and JESD204C converters from leading suppliers, including Analog Devices and Texas Instruments.
As AI expands into wireless infrastructure, aerospace, and medical imaging, systems require richer real-world data capture. This drives demand for converters with higher sample rates, resolution, and channel density, alongside increased requirements for real-time compute and memory bandwidth. The Achronix JESD204C IP core increases lane rates and payload efficiency while improving link robustness, maintaining full backward compatibility with JESD204B to help customers migrate legacy systems with minimal development risk.
"AI is creating new performance requirements in markets that have always depended on fast, precise data conversion," said Jay Aggarwal, Sr. Director, Product Marketing – Achronix. "Our JESD204C IP core combines a flexible, deterministic converter interface with the Speedster7t architecture's 112 Gbps SerDes, 2D network-on-chip, high-bandwidth GDDR6 memory interfaces and embedded machine learning processors. Customers can acquire, distribute, store and process more data in real time while retaining the adaptability of an FPGA platform."
High-Performance, Flexible JESD204C Connectivity
Designed for high-bandwidth, multi-channel converter systems, the Achronix JESD204C IP core supports:
- Scalable Throughput – Up to 32 Gbps per lane and a maximum of 32 lanes per link for high-speed ADC and DAC connectivity.
- Encoding and Error Correction – supports both 64b/66b and 8b/10b encoding, plus forward error correction (FEC), CRC-12, and CRC-3 modes.
- Phase-Coherent Synchronization – Subclass-1 with deterministic latency support for single- and multi-channel systems.
- Robust Integration – Flexible framing, integrated alignment and recovery features, and an AXI-Lite interface for straightforward control.
Speedster7t Architecture Connects Conversion, Memory, and AI Compute
Speedster7t FPGAs integrate 112 Gbps SerDes for the signal integrity needed for 32 Gbps JESD204C links. A 2D network-on-chip (NoC) delivers high-bandwidth transport across the device, reducing programmable-routing congestion and power consumption.
Speedster7t devices are the only FPGAs featuring embedded GDDR6 memory controllers, delivering up to 4 Tbps of aggregate bandwidth to buffer massive datasets for real-time signal processing and AI inference. Embedded machine learning processors (MLPs) accelerate digital signal processing at the data source, while the high-throughput PCI Express Gen5 interface enables the rapid transfer of processed data to host systems.
Target Markets
- Wireless Infrastructure (5G/6G) – Direct-RF transceivers, massive-MIMO, and AI-assisted spectrum optimization.
- Aerospace and Defense – Radar, electronic warfare, and synchronized multi-channel AI-assisted detection.
- Test and Measurement – High-bandwidth oscilloscopes, digitizers, and automated test equipment.
- Edge Processing and Acquisition – Medical imaging and scientific instrumentation combining high-rate sampling with real-time DSP.
Availability
The IP package includes a graphical interface in the Achronix ACE design environment, synthesizable VHDL/Verilog design files, templates, and example designs. Hardware-tested demonstrations feature configuration scripts for VectorPath® accelerator cards, plus complete simulation tools and testbenches.
The Achronix JESD204C IP core is available now for Speedster7t FPGAs. To support evaluation and system testing, Achronix offers a free, time-bound evaluation version of the IP core. For product documentation or to request an evaluation core, visit www.achronix.com or contact sales@achronix.com.
* * *