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Partnership

Achronix’s Next-Generation, 7nm FPGA Family Will Feature Micron’s Blazingly Fast GDDR6 Memory – To 4 Tbps and Beyond

Manoj Roge, VP of Strategic Planning & Business Development

Micron Technology announced today that its high-performance GDDR6 SDRAM (in volume production since June) will be the high-speed memory of choice for Achronix’s yet-to-be-announced, next-generation FPGA family,  making Achronix the world’s first FPGA vendor with announced GDDR6 support.

Speedcore eFPGA

Back to Basics: A Layman’s Introduction to the eFPGA

Alok Sanghavi, Sr. Marketing Manager

To answer the question of what an embedded field programmable gate array (eFPGA) is, we first have to answer the question of what is an FPGA.

To oversimplify. an FPGA is a chip that is able to rewire its internal workings in the field whenever instructed, and then operate at hardware (as opposed to software) speeds until such time as it is rewired again. This capability is known as field programmability.

Video

Check out our Recent Video on the Basics of eFPGA Acceleration

Alok Sanghavi, Sr. Marketing Manager

Our existing customers ask us some pretty big questions: “How can this technology implement a step-change in my specific process? How can Speedcore IP be integrated in my SoC? How can you increase the performance of my ASIC?” We revel in answering such questions.

However, when we first meet with a company interested in our embedded FPGA (eFPGA) IP, often the question is very simply, “At the most basic level, what can it do for me?” This question may be the most important one we’ll ever answer for them.

Speedcore FCU

Configuring your Speedcore eFPGA, Part 1: Configuration Interfaces

Volkan Oktem, Sr. Director of Application

Each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store the eFPGA’s configuration bits. Each Speedcore instance contains its own FPGA configuration unit (FCU) that initializes, configures, and manages the Speedcore eFPGA’s core logic array. For example, if you instantiate three Speedcore eFPGAs in your ASIC/SoC design, there will be three FCUs on the chip.

Speedcore Configuration

Configuring Your Speedcore eFPGA, Part 2: Configuration Time

Volkan Oktem, Sr. Director of Application

As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to program a bitstream into a Speedcore eFPGA depends on the configuration mode being used, the data width, clock frequency, and of course, the size of the configuration bitstream.

SoC Acceleration

Embedded FPGA – The Ultimate Accelerator

Kent Orthner, Systems Architect

An embedded FPGA (eFPGA) is an IP core that you integrate into your ASIC or SoC to get the benefits of programmable logic without the cost, but with better latency, throughput, and power characteristics. With an eFPGA, you define the quantity of look-up-tables (LUTs), registers, embedded memory, and DSP blocks. You can also control the aspect ratio, number of I/O ports, making tradeoffs between power and performance. Achronix delivers a GDS II representation of the Speedcore IP that you can integrate directly into your SoC or ASIC. We also provide you with a custom, full-featured version of our ACE design tools, that you can use to design, verify and program the functionality of the Speedcore eFPGA.

Automotive ASICs

Embedded FPGAs for Next-Generation Automotive ASICs

Bob SIller, Sr. Marketing Manager

For anyone who has looked at new cars lately, it's hard not to notice how quickly automotive electronics are advancing. Looking at automotive safety technology from just three years ago vs. today, you see a significant increase in the number of cameras to support applications such as surround-view display, driver distraction monitors, stereo vision cameras, forward-facing and multiple rearview cameras. Speedcore

FPGAs 2020s

FPGAs in the 2020s – The New Old Thing

Bob SIller, Director, Product Marketing

FPGAs are the new old thing in semiconductors today. Even though FPGAs are 35 years old, the next decade represents a growth opportunity that hasn’t been seen since the early 1990s. Why is this happening now?

Speedcore Instance

How Big Should your eFPGA be? Here are Some Hints.

Volkan Oktem, Sr. Director of Application

Once you’ve made the correct decision to add Speedcore eFPGA IP to your ASIC or SoC design, the next question you’ll need to answer is how large to make the eFPGA. That’s a multi-dimensional question because Speedcore eFPGAs contain many types of blocks including:

Automotive AI

How to Meet Self-Driving Automotive Design Goals Part 1

Manoj Roge, Vice President and Chief Technologist

Achronix anticipates that the favored self-driving architecture of the future will be increasingly decentralized. However, both the centralized and decentralized architectural design approaches will require hardware acceleration in the form of far more lookaside coprocessing than is currently realized.