Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

Select the individual tabs below to browse through each type of documentation. Or use the filter to only see documentation related to your product of interest.

Some documents are restricted (denoted by the lock symbol in the download button) and require a support portal account to access the download. To download a restricted document, enter your support portal account credentials when prompted. Don't have a support portal account? Register for an account here: Achronix Support Account Registration

Title Description Version Released Date Document File
How to Meet Power Performance and Cost for Autonomous Vehicle Systems using Speedcore eFPGAs (WP015)

In the advanced, fully autonomous, self-driving vehicles of the future, the existence of dozens and even hundreds of distributed CPUs and numerous other processing elements is assured. Peripheral sensor-fusion and other processing tasks can be served by ASICs, SoCs, or traditional FPGAs. But the introduction of embedded FPGA blocks such as Achronix's Speedcore eFPGA IP provides numerous system-design advantages in terms of shorter latency, more security, greater bandwidth, and better reliability that are simply not possible when using CPUs, GPUs, or even standalone FPGAs.

1.00 Download
Achieving ASIC Timing Closure with Speedcore eFPGAs (WP013)

Achronix's Speedcore eFPGA IP allows companies to embed a programmable logic fabric in their ASICs, delivering to end users the capability to modify or upgrade the functionality of an ASIC after being deployed in the field. This flexibility dramatically expands the solution space that can be served by the ASIC as it can be updated to support changing standards and algorithms. Timing closure is particularly challenging due to the fact that the eFPGA fabric may host any number of designs over the course of device operation. Each of those designs must work independently with the rest of the ASIC, and timing closure can only be said to have been met if all of the possible designs targeting the eFPGA fabric can meet timing.

1.00 Download
2018 Ushers in a Renewed Push to the Edge (WP012)

The past decade has seen massive growth in centralized computing, with data processing flowing to the cloud to take advantage of low-cost dedicated data centers. It was a trend that seemed at odds with the general trend in computing — a trend that started with the mainframe but moved progressively towards ambient intelligence and the internet of things (IoT). As we move into 2018, this centralization is reaching its limit. The volume of data that will be needed to drive the next wave of applications is beginning to force a change in direction.

1.00 Download
The Ideal Solution for AI Applications — Speedcore eFPGAs (WP011)

AI requires a careful balance of datapath performance, memory latency, and throughput that requires an approach based on pulling as much of the functionality as possible into an ASIC or SoC. But that single-chip device needs plasticity to be able to handle the changes in structure that are inevitable in machine-learning projects. Adding eFPGA technology provides the mixture of flexibility and support for custom logic that the market requires. Achronix provides not only the building blocks required for an AI-ready eFPGA solution, but also delivers a framework that supports design through to debug and test of the final application. Only Achronix Speedcore IP has the right mix of features for advanced AI that will support a new generation of real-time, self-learning systems.

1.00 Download
Enhancing eFPGA Functionality with Speedcore Custom Blocks (WP009)

Achronix Speedcore™ eFPGA IP can be integrated in an SoC for high-performance, compute-intensive and realtime processing applications such as AI, automotive sensor fusion, network acceleration and wireless 5G. Speedcore eFPGA IP is a game-changer for SoC developers, allowing them to add flexibility to their products by including FPGA technology in their ASICs. For SoC development, companies specify the quantity and mix of lookup-table (LUT) logic, embedded memory blocks, and DSP blocks that best meets their needs. Along with these functions, Achronix now offers the ability for companies to define custom block functions, optimized for their application, that can also be included in the eFPGA fabric. Speedcore custom blocks increase die area efficiency, increase performance and lower power.

1.00 Download
Title Description Version Released Date Document File
Speedster22i HD1000 FPGA Datasheet (DS005)

Speedster22i HD1000 devices run at a maximum rate of 750 MHz and have an effective density of up to one million LUTs. Based on the Intel 22nm process, Speedster22i HD1000 devices are SRAM based and fully reconfigurable.

1.20 Download
Speedster22i HD1000 Pin Table

The pin tables (in Excel format) for the Speedster22i AC22IHD1000 in the FBGA2597 and FBGA1932 packages.

1.90 Download
Title Description Version Released Date Document File
Running Achronix Tools on Ubuntu

The Achronix tool chain is formally supported for a number of operating systems (OSes) as listed in the ACE User Guide (UG001). For these OSes, Achronix guarantees operation, and each release of the tool is thoroughly tested on each of those platforms.

1.10 Running_Achronix_Tools_on_Ubuntu_AN006.pdf
Using Encrypted Source Files with ACE

Designers need a way to protect their source IP, and that is often achieved by way of encrypted RTL. Achronix's tool flow using ACE and SynplifyPro supports the use of encrypted IP to enable protection of all or part of an IP's RTL.

1.00 Using_Encrypted_Source_Files_with_ACE_AN008.pdf
ACE ECO Flow Guide

This tutorial serves as an introduce to the ACE engineering change order (ECO) suite — a set of Tcl commands that can add or remove instances, nets, pin connections, and more from a placed-and-routed design.

1.00 ACE_ECO_Flow_Guide_AN015.pdf
Pipelining the CPU Interface

A Speedcore instance hosted in an SoC supports three different configuration modes: CPU, serial flash and JTAG. In CPU mode, an external CPU acts as the master and controls the programming operations for the Speedcore eFPGA, and offers a high-speed method for loading configuration data.

1.00 Pipelining_the_CPU_Interface_AN016.pdf
Repeatability in ACE

One of the desired requirements of any FPGA design tool is the ability to reproduce the exact same results every time the tool is run under the same conditions — a requirement refereed to as repeatability. The ACE placer and router are deterministic, delivering 100% repeatability.

1.20 Repeatability_in_ACE_AN012.pdf
Title Description Version Released Date Document File
Speedcore eFPGA Product Brief (PB028)

Speedcore IP is embedded FPGA (eFPGA) that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements.

1.50 Download
PCIe Accelerator-6D Board (PB027)

The Achronix PCIe Accelerator-6D Board is the industry’s highest memory bandwidth, FPGA-based PCIe add-in card for high-speed acceleration applications.

1.60 Download
HD1000 Development Kit (PB025)

The HD1000 development kit is optimized for development of networking and communication sub-systems — with 100 Gbps throughput, and offers the appropriate ports and memory capacity for these functions.

2.70 Download
Speedster22i HD FPGA Platform (PB024)

The Speedster22i HD FPGAs have a synchronous architecture and are built on Intel’s advanced 22nm 3-D Tri-Gate transistor technology. Targeted for high-bandwidth communication applications, Speedster22i HD FPGAs offer the combination of the highest density with the lowest power consumption.

2.70 Download
Title Description Version Released Date Document File
Speedster7t IP Component Library User Guide (UG086)

The Achronix Speedster7t macro cell library provides the user with building blocks that may be instantiated into the user’s design. These macros provide access to low-level fabric primitives, complex I/O block, and higher level design components. Each library element entry describes the operation of the macro as well as any parameters that must be initialized. Verilog and VHDL templates are also provided to aide in the implementation of the user’s design.

0.90 Download
Speedster7t Network on Chip User Guide (UG089)

The Speedster7t FPGA family of devices has a network hierarchy that enables extremely high-speed dataflow between the FPGA core and the interfaces around the periphery, as well as between logic within the FPGA itself. This on-chip network hierarchy supports a cross-sectional bidirectional bandwidth of 20 Tbps. It supports a multitude of interface protocols including GDDR6, DDR4/5, 400G Ethernet, and PCI Express Gen5 data streams, while greatly simplifying access to memory and high-speed protocols. Achronix's network on chip (NoC) provides for read/write transactions throughout the device, as well as specialized support for 400G Ethernet streams in selected columns. The NoC extends both vertically and horizontally over the FPGA fabric until it reaches the peripheral portion of the NoC. This structure provides an easy-to-use, high-bandwidth method to communicate between various masters and slaves on a Speedster7t device, including specialized connections between the Ethernet subsystem and NoC access points (NAPs) on select NoC columns in the FPGA fabric. In addition, the NoC provides a connection from the FPGA fabric and IP interfaces to the FPGA configuration unit (FCU). The FCU receives bitstreams and is used to configure the FPGA fabric as well as the various IP interfaces on the device. The NoC also provides read and write access to the control and status register (CSR) space. The CSR space includes control registers and status registers for the IP interfaces. The features of the NoC described in this user guide generally pertain to the entire Speedster7t family of devices. In order to help users understand specific connections and features of the NoC, this user guide focuses on the NoC as implemented in the AC7t1500 device. 

1.00 Download
ACE User Guide for Speedster22i FPGAs (UG001)

This guide is a reference manual for the Achronix CAD Environment (ACE), used for placing, routing, configuring, and debugging Achronix FPGAs. ACE works in conjunction with third-party synthesis and simulation tools to provide a complete design environment for Achronix FPGAs.

7.20 Download
Speedster7t Reference Designs User Guide (UG085)

The following designs are a collection of reference designs that demonstrate some of the advanced features of the Speedster7t FPGA family. They are primarily focused on the machine learning processor (MLP) block which is tightly coupled with a block memory (BRAM). This block allows for up to 32 simultaneous multiplications in a single cycle, as well as supporting a wide collection of number formats from floating point to 16 bit integer. The designs have all been run through Synplify-Pro and ACE, and where applicable expected performance and resource utilization values are given. In addition, all of the designs include a simulation environment to allow the user to verify the correct operation. The designs are provided "as-is", with no warranty with regard to fitness of purpose, or direct applicability to a users solution. Users are encouraged to test the designs and then to modify to suit their particular solution needs. With regard to detailed specifics as to how particular blocks function, the comments in the code can be consulted; alternatively simulation of the design will additionally show the functionality.
 

1.10 Download
Speedster7t Machine Learning Processing User Guide (UG088)

The machine learning processing block (MLP) is an array of up to 32 multipliers, followed by an adder tree, an accumulator, and a rounding/saturation/normalize block.The MLP also includes two memory blocks, a BRAM72k and LRAM2k, that can be used individually or in conjunction with the array of multipliers. The number of multipliers available varies with the bit width of each operand and the total width of input data. When the MLP is used in conjunction with a BRAM72k, the amount of data inputs to the MLP block increases along with the number of multipliers available. 

0.90 Download