Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity (WP017)

Intelligent server adapters, or SmartNICs, boost server performance in cloud and private data centers by offloading network processing workloads and tasks from server CPUs. Offloading network processing to a SmartNIC is not a new concept — for example, there are NICs that offload some network-processing functions such as checksum computation and segmentation. However, the rapid explosion in data-center network traffic driven by software-defined networking (SDN), Open vSwitch (OVS), and network functions virtualization (NFV) demands a new class of NIC with even greater offload capabilities: the SmartNIC.

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Chiplets - Taking SoC Design Where no Monolithic IC has Gone Before (WP016)

The well-documented slowing of Moore's Law is the key driver behind the movement towards the use of chiplets in the design and manufacture of new, high-performance semiconductor devices. While the monolithic IC has been the ultimate design target for many decades, there have always been reasons to build certain devices with multiple die using multi-chip modules (MCMs), whether it was for additional memory capacity or to fabricate chips based on IP blocks that require incompatible IC processes.

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Mine Cryptocurrencies Sooner, Faster, and Cheaper with Achronix Speedcore Embedded FPGAs (WP014)

New cryptocurrencies such as Monero introduce ASIC-resistance and memory-hardness to prevent ASICs from being built that give some operators a competitive mining advantage over others who do not have access to the same technology. This white paper discusses the relevant background and presents a solution based on Achronix Speedcore™ embedded FPGAs (eFPGAs), enabling users to regain a highly profitable advantage over competing solutions.

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How to Meet Power Performance and Cost for Autonomous Vehicle Systems using Speedcore eFPGAs (WP015)

In the advanced, fully autonomous, self-driving vehicles of the future, the existence of dozens and even hundreds of distributed CPUs and numerous other processing elements is assured. Peripheral sensor-fusion and other processing tasks can be served by ASICs, SoCs, or traditional FPGAs. But the introduction of embedded FPGA blocks such as Achronix's Speedcore eFPGA IP provides numerous system-design advantages in terms of shorter latency, more security, greater bandwidth, and better reliability that are simply not possible when using CPUs, GPUs, or even standalone FPGAs.

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Achieving ASIC Timing Closure with Speedcore eFPGAs (WP013)

Achronix's Speedcore eFPGA IP allows companies to embed a programmable logic fabric in their ASICs, delivering to end users the capability to modify or upgrade the functionality of an ASIC after being deployed in the field. This flexibility dramatically expands the solution space that can be served by the ASIC as it can be updated to support changing standards and algorithms. Timing closure is particularly challenging due to the fact that the eFPGA fabric may host any number of designs over the course of device operation. Each of those designs must work independently with the rest of the ASIC, and timing closure can only be said to have been met if all of the possible designs targeting the eFPGA fabric can meet timing.

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Title Description Version Released Date Document File
Production Testing of Speedcore eFPGAs (AN017)

The robustness of ATE production testing is critical to the success and quality of Speedcore eFPGAs. The overall objectives in the implementation and delivery are to reach coverage metrics and allow for industrystandard DPM targets to be met at minimal cost.

1.0 Production_Testing_of_Speedcore_eFPGAs_AN017.pdf
Running Achronix Tools on Ubuntu (AN006)

The Achronix tool chain is formally supported for a number of operating systems (OSes) as listed in the ACE User Guide (UG001). For these OSes, Achronix guarantees operation, and each release of the tool is thoroughly tested on each of those platforms.

1.1 Running_Achronix_Tools_on_Ubuntu_AN006.pdf
Migrating to Achronix eFPGA Technology (AN014)

Many users transitioning to Achronix eFPGA technology will be familiar with existing FPGA solutions from other vendors. Although Achronix technology and tools are similar to existing FPGA technology and tools, there are some differences. Understanding these differences are needed to achieve the very best performance and quality of results (QoR).

1.1 Migrating_to_Achronix_eFPGA_Technology_AN014.pdf
Using Encrypted Source Files with ACE (AN008)

Designers need a way to protect their source IP, and that is often achieved by way of encrypted RTL. Achronix's tool flow using ACE and SynplifyPro supports the use of encrypted IP to enable protection of all or part of an IP's RTL.

1.0 Using_Encrypted_Source_Files_with_ACE_AN008.pdf
ACE ECO Flow Guide (AN015)

This tutorial serves as an introduce to the ACE engineering change order (ECO) suite — a set of Tcl commands that can add or remove instances, nets, pin connections, and more from a placed-and-routed design.

1.0 ACE_ECO_Flow_Guide_AN015.pdf
Title Description Version Released Date Document File
Speedcore eFPGA Test Chip Evaluation Board (PB030)

The Speedcore eFPGA evaluation board from Achronix contains the 16-nm Speedcore eFPGA test chip. The evaluation board’s Speedcore test chip has been customized with the right blend of resources such as LUTs, BRAMs, DSP64s, DFFs and a number of I/O so as to provide an optimum programmable platform for demonstrating, evaluating and testing Achronix’s Speedcore technology.

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Title Description Version Released Date Document File
Speedcore DFT and Test User Guide (UG067)

Design for test (DFT) is an important consideration for Speedcore eFPGAs from the perspective of both Achronix and the ASIC integrator. The programmable nature of Speedcore eFPGAs deliver the inherent benefit of being able to use the programmable logic fabric to test itself. This guide describes Speedcore eFPGAs from a testability perspective and outlines the general features and methodologies that Achronix uses to achieve the necessary coverage.

1.4 Speedcore_DFT_and_Test_User_Guide_UG067.pdf
Speedster7t Network on Chip User Guide (UG089)

The Speedster7t FPGA family of devices has a network hierarchy that enables extremely high-speed dataflow between the FPGA core and the interfaces around the periphery, as well as between logic within the FPGA itself. This on-chip network hierarchy supports a cross-sectional bidirectional bandwidth of 20 Tbps. It supports a multitude of interface protocols including GDDR6, DDR4/5, 400G Ethernet, and PCI Express Gen5 data streams, while greatly simplifying access to memory and high-speed protocols. Achronix's network on chip (NoC) provides for read/write transactions throughout the device, as well as specialized support for 400G Ethernet streams in selected columns. The features of the NoC described in this user guide generally pertain to the entire Speedster7t family of devices. In order to help users understand specific connections and features of the NoC, this user guide focuses on the NoC as implemented in the AC7t1500 device.

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Speedster7t Pin Connectivity User Guide (UG084)

This user guide lists each of the I/O pin groups available in the Speedster7t 7t1500 device, their functionality and recommended connection guidelines. Refer to the Power User Guide for detailed description on the power/gnd pins

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Speedster7t Clock and Reset Architecture User Guide (UG083)

Achronix’s new 7nm Speedster 7t FPGA family is specifically designed to deliver extremely high performance for ® demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center. In order to meet the demand of high performance and complex designs, the clock network for Speedster7t FPGAs has been designed with numerous high performance clocks that allow for maximum routability. This document explains the architecture of the different clock networks in a Speedster7t FPGA, as well as information on how to use the clocks. It is intended to help designers understand and choose the best clocking options for their design on a Speedster7t FPGA.

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Speedster7t GDDR6 User Guide (UG091)

The Speedster7t FPGA device family provides multiple GDDR6 subsystems that enables the user to fully utilize the high-bandwidth efficiency of these interfaces for critical applications such as high-performance compute and machine learning systems.The number of GDDR6 subsystems varies with Speedster7t device. Each subsystem comprises the GDDR6 controller and PHY hard cores and supports up to 512 Gbps; as a result, the 7t1500 offers up to 4 Tbps of total bandwidth. The GDDR6 controller and PHY in the subsystem are implemented as hard IP blocks in the I/O ring of a Speedster7t FPGA.

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