Achronix Integrated Design Software (ACE)

Achronix ACE FPGA Design Software is an integrated design environment and your key to unlocking the full potential of Achronix FPGAs, including Speedster®7t FPGAs and Speedcore® eFPGA IP. Designed to provide a streamlined, powerful design flow, ACE equips FPGA developers with industry-leading tools, features, and solutions, optimized for high performance and ease of use.

Whether designing for a Speedster7t FPGA or an ASIC with embedded Speedcore eFPGA IP, Achronix ACE delivers superior performance with enhanced functionality across every stage of the design process.

Key Features of Achronix ACE

1. Comprehensive FPGA Design Flow

ACE integrates all aspects of FPGA design under one intuitive platform:

• Design Capture and IP Configuration – Easily manage design files and configurations
• Integrated Simulation – Broad support for industry-standard simulation tools
• Integrated Synthesis - Highly optimized synthesis engine, leveraging a custom Achronix OEM version of Synplify Pro under the hood
• Place and Route – Achieve superior results with Achronix's state-of-the-art proprietary algorithms optimized for performance
• Optimization and Timing Closure – Meet performance goals with advanced timing analysis, power optimization, physical synthesis, and floor-planning tools

2. Optimized for Maximum Performance

ACE software is meticulously tuned to deliver the highest levels of:

• Performance – Push your designs to achieve the highest operational frequencies (f_MAX) with the most area efficient placement
• Runtime Efficiency – Drastically reduce compile times with multi-process optimizations
• Memory Utilization – Minimized memory footprint for smoother workflows
• Automation - Intelligent multi-variable parallel design compile

3. Advanced Productivity Features

Save time and accelerate your design turn around time using innovative new features:

• I/O Designer – Real-time configuration, design rule checking, and timing closure for all I/O types in minutes (GPIO, PCIe, Ethernet, raw SerDes, 2D NoC, GDDR6, DDR5, etc.)
• Device Simulation Model - Simplifies design complexity to get your chip-level simulations up and running quickly, fully integrated with I/O Designer
• 2D NoC-based Partial Reconfiguration - Eliminates major challenges of traditional partial reconfiguration design efforts using NoC access points (NAPs), with fast bitstream load over PCIe
• Incremental Compile Flow - Reduce runtime on design iterations with incremental synthesis, placement, and routing
• Advanced Design Re-Use - Leverage the power of partition export/import and the Achronix-patented copy-paste-move feature

4. Advanced Design Debugging Support

ACE provides a variety of cutting-edge tools to help you debug your design quickly:

• Live DRC checking - Upfront, real-time IP configuration rule checking, plus advanced simulation model cross-checks throughout the libraries
• Snapshot Debugger – Perform in-depth debugging with the Snapshot Debugger tool and JTAG TCL API
• 2D NoC Performance View – Visualize and alleviate any bottlenecks in 2D NoC throughput and performance using simulation data
• SerDes Analysis - Integrated push-button SerDes eye diagram plotting and TCL-based debug API

5. Software Customization

Extend and customize ACE to enhance your application-specific, end-user experience:

• Customizable Flow - Add your own custom flow steps into ACE to generate user-defined tasks, checks, and reports
• IP Generator Plugin Framework – Plug in your own custom soft IP, or third-party soft IP, to seamlessly extend the built-in ACE libraries, including GUI support
• Hardware Demo Framework - Build your own custom GUIs that connect to the FPGA hardware to display live graphs, status, and more

6. Quality, Support, and Flexibility

The entire ACE tool chain is built from the ground up to ensure stability and a high-quality user experience:

• Support for a wide variety of Linux and Windows operating systems
• Rigorous testing and regression infrastructure at all levels, across all OSes, devices, features, and flows to ensure ACE meets the highest standards of quality with built-in formal verification
• Long history of regular ongoing software release cadence, producing multiple major, minor, and patch releases each year
• Our top-notch multi-tier customer support team and infrastructure is ready to help you along the way

7. Unified Tools for Speedcore and Speedster Devices

Leverage the same powerful tools for designing with both Speedster FPGAs and Speedcore eFPGA IP, providing a seamless design experience:

• Design Reuse - Easily port designs between Speedster and Speedcore architectures, maximizing flexibility and reducing development effort
• Reduced Learning Curve - Simplifies adoption by offering the same toolset for both device types

Additional Tools and Resources

High-Level Synthesis (Coming in 2025) 

Utilize high-level synthesis (HLS) tools to accelerate the design process and generate efficient hardware code from C-based designs:

• Increased Productivity – Simplify the design process by using familiar high-level programming languages such as C, C++, or SystemC.
• Optimized Hardware Implementation – Automatically generate RTL code optimized for performance, area, and power from high-level abstractions.
• Shortened Development Cycles – Reduce the time-to-market by abstracting complex HDL coding tasks.
• Improved Collaboration – Allow software and hardware teams to work more cohesively using a common design framework.

Achronix PCIe Software Development Kit (SDK)

Enables developers to write host-side applications that communicate with and control their designs using the PCIe interface. This SDK consists of:

• A C-based application programming interface (API) at multiple levels of abstraction for code simplicity vs. performance tradeoffs
• A native Linux PCIe device driver
• Examples, utility applications, and documentation in HTML and PDF formats

The complete API and device driver are supplied in source code form, with extensive documentation, to  jump-start your own development projects. Supported features include:

• Memory-mapped reads and writes to all on-chip and off-chip memories, as well as all hard IP configuration/status registers, across a single unified 2D NoC address space
• Gather-scatter DMA with or without descriptor lists
• MSI-X configuration and interrupt service routines
• Fast device configuration over PCIe including support for encrypted bitstreams
• Partial reconfiguration over PCIe

Reference Designs and Soft IP

Access a rich library of reference designs and soft IP to kick-start your FPGA projects:

• Speed up your design process using configurable soft IP, from basic building blocks such as BRAMs to FIR filters and the Achronix ANIC.
• Get up and running out of the box with reference designs showcasing all of the major IP, from the 2D NoC and MLPs to PCIe, GDDR6, and Ethernet.

Documentation and Support Resources

Comprehensive support documentation available, including:

• Extensive User Guides – Detailed step-by-step instructions.
• Built-in Help System – Searchable, dynamic, and context-aware.
• Application Notes and White Papers – Dive deeper into FPGA design with a wide array of resources.
• Reference Designs and Tutorials – Access tutorials and example designs to guide you through your projects.

The Achronix ACE Advantage

Backed by nearly two decades of continuous innovation, Achronix ACE is designed to empower FPGA designers of high-speed systems to deliver unmatched efficiency, power, and speed in the shortest amount of time. Its wide range of features ensures that ACE delivers:

• Easy Integration – Transition smoothly from other FPGA tool-chains
• Advanced Capabilities – Take advantage of unique features such as partial reconfiguration, IP plugins, and 2D NoC performance analysis
• High Reliability – Rock-solid architecture tested rigorously for stability and performance.