September 13, 2022
FPGA World focuses on user-oriented, practically applicable FPGA solutions that developers can quickly integrate into their everyday work.
Meet Achronix at our booth or contact us to arrange a meeting. We will be showcasing our FPGA technologies built for acceleration of AI, ML, networking, data center automotive and other HPC applications.
- VectorPath® Accelerator Cards: PCIe accelerator cards for rapid prototyping and production. Offers 400G and 200G Ethernet interfaces and 4 Tbps of GDDR6 memory bandwidth.
- Speedster®7t FPGAs: high-performance FPGAs with a 2D network on chip. Delivers ASIC-level performance with the full programmability of FPGAs.
- Speedcore™ eFPGA IP: 15+ million eFPGA IP cores shipped. Brings the performance and flexibility of programmable logic to ASICs and SoCs.
We will be showing a demonstration of our two-dimensional network on chip (2D NoC). Truly 2D, the NoC has access points located throughout the FPGA core that provide an aggregate of 20 Tbps of bandwidth for interfacing to off-chip resources such as GDDR6 and DDR4 memories, PCI Express interfaces and 400GbE ports, internal hard IP blocks such as the machine learning processors and the FPGA fabric itself. This superhighway is unparalleled in the industry, leading to the fastest FPGA in the market.
Tuesday, September 13, 10:30–11:00am
"Maximize External Memory Bandwidth Efficiency with Any Access Pattern"
Raymond Nijssen, VP and Chief Technologist
This presentation details how to manage bandwidth limitations and leverage FPGA features so that the effective DRAM bandwidth efficiency can be close to the theoretical upper limit, even with worst-case access patterns. The presentation shows how this efficiency can be easily achieved with practical FPGA designs using the GDDR6 memory subsystem and the high-bandwidth 2D NoC found in Achronix Speedster7t FPGAs.
Meet with Achronix
Achronix is interested to hear about your next project! Contact us and let us know about your design challenge. We can discuss a customizable approach that can eliminate bottlenecks and significantly reduce engineering time of your next ASIC or SoC.