FPGA Conference Europe 2022

Event Start Date
Event End Date
NH München Ost Conference Center

July 5–7, 2022
Munich, Germany

FPGAs have made an evolutionary leap forward in terms of new approaches and solutions for both hardware and software developers. FPGA Conference Europe 2022 is addressing that progress across all major chip manufacturers. The conference focuses on user-oriented, practically applicable solutions that developers can quickly integrate into their own everyday work.

See Us in Booth 9

Meet Achronix at our booth or contact us to arrange a meeting. We'll be showcasing our FPGA technologies built for acceleration of AI, ML, networking, data center automotive and other HPC applications.

  • Speedster®7t FPGAs: high-performance FPGAs with a 2D network on chip. Delivers ASIC-level performance with the full programmability of FPGAs.
  • Speedcore™ eFPGA IP: 15+ million eFPGA IP cores shipped. Brings the performance and flexibility of programmable logic to ASICs and SoCs.
  • VectorPath® Accelerator Cards: PCIe accelerator cards for rapid prototyping and production. Offers 400G and 200G Ethernet interfaces and 4 Tbps of GDDR6 memory bandwidth.


Stop by our booth for a demonstration of our two-dimensional network on chip (2D NoC). Truly 2D, the NoC has access points located throughout the FPGA core that provide an aggregate of 20 Tbps of bandwidth for interfacing to off-chip resources such as GDDR6 and DDR4 memories, PCI Express interfaces and 400GbE ports, internal hard IP blocks such as the machine learning processors and the FPGA fabric itself. This superhighway is unparalleled in the industry, leading to the fastest FPGA in the market.


Don’t miss this expert presentation from Raymond Nijssen, VP and Chief Technologist!

Wednesday, July 6, 9:45am–10:30am
Track 2: Board-Level & Connectivity

Raymond Nijssen

Maximize External Memory Bandwidth Efficiency with Any Access Pattern

This presentation details how to manage bandwidth limitations and leverage FPGA features so that the effective DRAM bandwidth efficiency can be close to the theoretical upper limit, even with worst-case access patterns. It showcases how this can be easily achieved with practical FPGA designs using the GDDR6 memory subsystem and the high-bandwidth 2D NoC found in Achronix Speedster7t FPGAs.

Read the full abstract here.

Contact us to arrange a meeting or private demo. We will be happy to discuss your project and how Achronix can help achieve your performance and go-to-market goals.