The Achronix Blog

Speedcore eFPGA Enable Increased Security in Networks Solution on the Edge

Next-generation networking solutions are pushing processing out of the cloud and towards the network’s edge. At the same time, processing structures architected around programmable logic provide the ability to make computing much more data-centric. Programmable logic makes it possible to construct data pipelines versus traditional processors demand for data to be fed to their pipelines through a complex hierarchy of memory caches.

Next-Generation AI Hardware needs to be Flexible and Programmable

Artificial intelligence (AI) is reshaping the way the world works, opening up countless opportunities in commercial and industrial systems. Applications span diverse markets such as autonomous driving, medical diagnostics, home appliances, industrial automation, adaptive websites and financial analytics. Even the communications infrastructure linking these systems together is moving towards automated self-repair and optimization.

Visitors to CES 2018 will Experience the Future of Transportation

When visitors to CES 2018 want to travel to the Las Vegas Convention Center across town, it will likely be in a fully autonomous vehicle from Lyft getting them there. While this futurist trip will certainly be a first for many riders, this type of point-to-point travel will soon become commonplace. But questions concerning the safety of autonomous vehicles remain. For Lyft's CES demonstration, a backup pilot will be in the driver's seat for added safety.

Why Designers Need to Look Towards Combining CPUs with FPGA Fabrics

Given that the industry is beginning to reach the limits of what can physically and economically be achieved through further shrinkage of process geometries, reducing feature size and increasing transistor counts is no longer achieving the same result it once did. Instead the industry is, quite rightly, focusing on fundamentally new system architectures and making better use of available silicon through radical rethinking of how tasks are achieved within each device.

Check out our Recent Video on the Basics of eFPGA Acceleration

Our existing customers ask us some pretty big questions: “How can this technology implement a step-change in my specific process? How can Speedcore IP be integrated in my SoC? How can you increase the performance of my ASIC?” We revel in answering such questions.

However, when we first meet with a company interested in our embedded FPGA (eFPGA) IP, often the question is very simply, “At the most basic level, what can it do for me?” This question may be the most important one we’ll ever answer for them.

Who’s Who in the Zoo

While the concept of eFPGA IP is fairly straightforward, the number of parties involved and their responsibilities may not be clear at the outset. It is the very programmable nature of an eFPGA that can cause confusion of who is responsible for what. With a standalone FPGA, there are three parties involved: the FPGA vendor, the foundry and the end user. The relationships between each are straightforward and well understood. Communication happens between the FPGA vendor and its foundry, but not between the end user and the foundry.

Back to Basics: A Layman’s Introduction to the eFPGA

To answer the question of what an embedded field programmable gate array (eFPGA) is, we first have to answer the question of what is an FPGA.

To oversimplify. an FPGA is a chip that is able to rewire its internal workings in the field whenever instructed, and then operate at hardware (as opposed to software) speeds until such time as it is rewired again. This capability is known as field programmability.

Embedded FPGA – The Ultimate Accelerator

An embedded FPGA (eFPGA) is an IP core that you integrate into your ASIC or SoC to get the benefits of programmable logic without the cost, but with better latency, throughput, and power characteristics. With an eFPGA, you define the quantity of look-up-tables (LUTs), registers, embedded memory, and DSP blocks. You can also control the aspect ratio, number of I/O ports, making tradeoffs between power and performance. Achronix delivers a GDS II representation of the Speedcore IP that you can integrate directly into your SoC or ASIC. We also provide you with a custom, full-featured version of our ACE design tools, that you can use to design, verify and program the functionality of the Speedcore eFPGA.