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Check out our Recent Video on the Basics of eFPGA Acceleration

Alok Sanghavi,Sr. Marketing Manager

Our existing customers ask us some pretty big questions: “How can this technology implement a step-change in my specific process? How can Speedcore IP be integrated in my SoC? How can you increase the performance of my ASIC?” We revel in answering such questions.

However, when we first meet with a company interested in our embedded FPGA (eFPGA) IP, often the question is very simply, “At the most basic level, what can it do for me?” This question may be the most important one we’ll ever answer for them.

Speedcore Engagement

Who’s Who in the Zoo

Steve Mensor,Vice President, Marketing

While the concept of eFPGA IP is fairly straightforward, the number of parties involved and their responsibilities may not be clear at the outset. It is the very programmable nature of an eFPGA that can cause confusion of who is responsible for what. With a standalone FPGA, there are three parties involved: the FPGA vendor, the foundry and the end user. The relationships between each are straightforward and well understood. Communication happens between the FPGA vendor and its foundry, but not between the end user and the foundry.

Speedcore eFPGA

Back to Basics: A Layman’s Introduction to the eFPGA

Alok Sanghavi,Sr. Marketing Manager

To answer the question of what an embedded field programmable gate array (eFPGA) is, we first have to answer the question of what is an FPGA.

To oversimplify. an FPGA is a chip that is able to rewire its internal workings in the field whenever instructed, and then operate at hardware (as opposed to software) speeds until such time as it is rewired again. This capability is known as field programmability.

SoC Acceleration

Embedded FPGA – The Ultimate Accelerator

Kent Orthner,Systems Architect

An embedded FPGA (eFPGA) is an IP core that you integrate into your ASIC or SoC to get the benefits of programmable logic without the cost, but with better latency, throughput, and power characteristics. With an eFPGA, you define the quantity of look-up-tables (LUTs), registers, embedded memory, and DSP blocks. You can also control the aspect ratio, number of I/O ports, making tradeoffs between power and performance. Achronix delivers a GDS II representation of the Speedcore IP that you can integrate directly into your SoC or ASIC. We also provide you with a custom, full-featured version of our ACE design tools, that you can use to design, verify and program the functionality of the Speedcore eFPGA.