The Achronix Blog

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FPGAs 2020s

FPGAs in the 2020s – The New Old Thing

Bob SIller,Director, Product Marketing

FPGAs are the new old thing in semiconductors today. Even though FPGAs are 35 years old, the next decade represents a growth opportunity that hasn’t been seen since the early 1990s. Why is this happening now?

Cryptocurrency Mining ASIC Top Level

Mine Cryptocurrencies Sooner Part 3

Raymond Nijssen,Vice President and Chief Technologist

New, post-Bitcoin cryptocurrencies have been developed with ASIC resistance to level the competitive playing field for cryptocurrency miners, as discussed in parts 1 and 2 of this blog. ASIC resistance was developed to counteract monopolization of cryptocurrencies by the few entities that can afford to build ASIC solutions, as has happened with Bitcoin. However, ASIC resistance does not ensure the necessary scarcity of a cryptocurrency.


Mine Cryptocurrencies Sooner Part 2

Raymond Nijssen,Vice President and Chief Technologist

Bitcoin has lost much of its allure due to the concentration of control of the world’s Bitcoin mining resources by a few players in a few locations, as discussed in Part 1 of this blog. In response, the larger, global cryptocurrency community has started to develop alternative cryptocurrencies based on lessons learned from the Bitcoin experience.

Cryptocurrency Mining

Mine Cryptocurrencies Sooner Part 1

Raymond Nijssen,Vice President, Marketing

Cryptocurrency mining is the process of computing a new cryptocurrency unit based on all the previously found ones. The concept of cryptocurrency is nearly universally recognized by the publicity of the original cryptocurrency, Bitcoin. Cryptocurrencies were supposed to be a broadly democratic currency vehicle not controlled by any one entity, such as banks, governments, or small groups of companies. Much of a cryptocurrency’s acceptance and trustworthiness is based on that proposition. However, with Bitcoin, that is not how it unfolded.


How to Meet Self-Driving Automotive Design Goals Part 2

Manoj Roge,VP of Strategic Planning & Business Development

Today, the advanced driver-assistance systems (ADAS) processor market is growing by more than 25% per year. This growth is driven by the migration of ADAS features – including automatic emergency braking, lane-changing assist, and adaptive cruise-control functions – from luxury vehicles to midrange and even entry-level vehicles. ADAS features will be almost universal by the middle of the next decade.

Automotive AI

How to Meet Self-Driving Automotive Design Goals Part 1

Manoj Roge,Vice President and Chief Technologist

Achronix anticipates that the favored self-driving architecture of the future will be increasingly decentralized. However, both the centralized and decentralized architectural design approaches will require hardware acceleration in the form of far more lookaside coprocessing than is currently realized.

360 Degree

Speedcore eFPGAs are an Enabling Technology for 360° Surround-view Systems

Alok Sanghavi,Sr. Marketing Manager

Next-generation video applications such as surveillance, object detection, motion analysis now rely on 360° embedded vision. In these systems, multiple real-time camera streams (up to six) are processed together frame by frame, with each frame corrected for distortion and other image artifacts, adjusted for exposure and white balance, and then stitched together dynamically into a single 360° panoramic view, then output at 4K 60 fps and ultimately projected on a spherical coordinate space.


Achronix’s Next-Generation, 7nm FPGA Family Will Feature Micron’s Blazingly Fast GDDR6 Memory – To 4 Tbps and Beyond

Manoj Roge,VP of Strategic Planning & Business Development

Micron Technology announced today that its high-performance GDDR6 SDRAM (in volume production since June) will be the high-speed memory of choice for Achronix’s yet-to-be-announced, next-generation FPGA family,  making Achronix the world’s first FPGA vendor with announced GDDR6 support.

Speedcore Timing

Learning to Share - Embedded FPGA Timing Closure

Alok Sanghavi,Sr. Marketing Manager

When we start school as young children, one of the first lessons we learn is how to share (followed quickly by not running with scissors). As our Sr. Director of Systems Engineering, Kent Orthner, discussed at DAC this past June, sharing is also key when it comes to closing timing with embedded FPGAs (eFPGAs). With an eFPGA such as Speedcore IP, the task of closing timing is owned by two people: the ASIC designer, responsible for the design in the host ASIC, and the FPGA designer, responsible for the design targeting the FPGA.

Speedcore Configuration

Configuring Your Speedcore eFPGA, Part 2: Configuration Time

Volkan Oktem,Sr. Director of Application

As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to program a bitstream into a Speedcore eFPGA depends on the configuration mode being used, the data width, clock frequency, and of course, the size of the configuration bitstream.