Speedster7t Clock and Reset Architecture User Guide (UG083)

Description

Achronix’s new 7nm Speedster 7t FPGA family is specifically designed to deliver extremely high performance for ® demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center. In order to meet the demand of high performance and complex designs, the clock network for Speedster7t FPGAs has been designed with numerous high performance clocks that allow for maximum routability. This document explains the architecture of the different clock networks in a Speedster7t FPGA, as well as information on how to use the clocks. It is intended to help designers understand and choose the best clocking options for their design on a Speedster7t FPGA.

Version
1.1
Released Date
2020-05-06