Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
Evaluating Speedcore IP For Your ASIC (WP007)

Phase zero is the beginning of a Speedcore design and how you begin matters. From a technical perspective, you will want to explore the possibilities to maximize the benefit of having your ASIC deployed with a Speedcore instance with a mix of resources well suited to your current and future programmed configurations. Achronix will help you along this road, providing support, training and feedback in employing tools, benchmarking designs and dealing with optimization issues.

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EFPGA Acceleration in SoCs — Understanding the Speedcore IP Design Process (WP008)

The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedded in an ASIC, are available to an ASIC development team either as products of the ACE design tools or as deliverables provided by Achronix. This methodology has already been proven in silicon and readily accommodates variations and preferences in company-specific ASIC development methodologies.

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Embedded FPGA – a New System-Level Programming Paradigm (WP006)

The current public debate on the future of the semiconductor industry has turned to discussions about a growing selection of technologies that focuses instead on new system architectures and better use of available silicon through new concepts in circuit, device, and packaging design. The emergence of embedded FPGA is, in fact, not only essential at this juncture of the microelectronics history, but also inevitable. To understand this, a review of the history of FPGA technology is in order.

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Using FPGAs to Accelerate Data Centers (WP005)

With the technology industry at a crossroads — the effective repeal of Moore's Law  — data centers have become the sweet spot of the technology sector, showing healthy revenue growth and attracting new system solutions in both hardware and software. Unlike the ethereal promise of upcoming wonders from AI, robotics and the IoT, data center growth and innovation is happening in the here and now, with an even brighter future ahead the moment other nascent markets emerge from their chrysalis with killer apps of their own.

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Title Description Version Released Date Document File
Speedster7t Clock and Reset Architecture User Guide (UG083)

Achronix’s new 7nm Speedster 7t FPGA family is specifically designed to deliver extremely high performance for ® demanding applications including data-center workloads and networking infrastructure. The processing tasks associated with these high-performance applications, specifically those associated with artificial intelligence and machine learning (AI/ML) and high-speed networking, represent some of the most demanding processing workloads in the data center. In order to meet the demand of high performance and complex designs, the clock network for Speedster7t FPGAs has been designed with numerous high performance clocks that allow for maximum routability. This document explains the architecture of the different clock networks in a Speedster7t FPGA, as well as information on how to use the clocks. It is intended to help designers understand and choose the best clocking options for their design on a Speedster7t FPGA.

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Speedster7t GDDR6 User Guide (UG091)

The Speedster7t FPGA device family provides multiple GDDR6 subsystems that enables the user to fully utilize the high-bandwidth efficiency of these interfaces for critical applications such as high-performance compute and machine learning systems.The number of GDDR6 subsystems varies with Speedster7t device. Each subsystem comprises the GDDR6 controller and PHY hard cores and supports up to 512 Gbps; as a result, the 7t1500 offers up to 4 Tbps of total bandwidth. The GDDR6 controller and PHY in the subsystem are implemented as hard IP blocks in the I/O ring of a Speedster7t FPGA.

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Simulation User Guide (UG072)

The Achronix tool suite includes synthesis and place-and-route software that maps RTL designs (VHDL or Verilog) into Achronix devices. In addition to synthesis and place-and-route functions, the Achronix software tools flow also supports simulation at several flow steps (RTL, Synthesized Netlist, and Post Place-And-Routed Netlist). This guide covers the simulation flow for Achronix devices.

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Speedster7t DDR User Guide (UG096)

The Achronix Speedster7t FPGA family provides DDR subsystems that enable the user to fully utilize the low latency and high-bandwidth efficiency of these interfaces for critical applications such as high-performance compute and machine learning systems. The DDR subsystem supports memory devices and features compliant with JEDEC Standard JESD79-4B.

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Speedster7t Machine Learning Processing User Guide (UG088)

The machine learning processing block (MLP) is an array of up to 32 multipliers, followed by an adder tree, an accumulator, and a rounding/saturation/normalize block.The MLP also includes two memory blocks, a BRAM72k and LRAM2k, that can be used individually or in conjunction with the array of multipliers. The number of multipliers available varies with the bit width of each operand and the total width of input data. When the MLP is used in conjunction with a BRAM72k, the amount of data inputs to the MLP block increases along with the number of multipliers available. 

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