Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

Select the individual tabs below to browse through each type of documentation. Or use the filter to only see documentation related to your product of interest.

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Title Description Version Released Date Document File
Speedster22i DDR3 User Guide (UG031)

Speedster22i DDR3 User Guide (UG031)

3.0 Download
Snapshot User Guide (UG016)

Snapshot is the real-time design debugging tool for Achronix FPGAs and cores. The Snapshot debugger, which is embedded in the ACE software, delivers a practical platform to observe the signals of a user's design in real-time. To use the Snapshot debugger, the Snapshot macro needs to be instantiated inside the user's RTL. After instantiating the macro and programming the device, the user will be able to debug the design through the Snapshot Debugger GUI within ACE, or via the run_snapshotTCL command API.

2.1 Download
Speedcore ASIC Integration and Timing User Guide (UG064)

This guide details the design flow for integrating a Speedcore eFPGA into an ASIC, including closing timing across the boundary between the Speedcore instance and the surrounding host ASIC, along with how to perform full-chip simulation.

1.1 Download
Speedcore Clock and Reset Architecture User Guide (UG063)

This user guide details the clock structure for a Speedcore instance, covering the global core clock network, and interface clock networks. This guide also covers various clocking scenarios and their impact on timing closure.

1.6 Download
Speedcore Power User Guide (UG066)

The power user guide covers the Achronix default power and signal integrity sign-off methodology with all relevant sign-off conditions. Also covered are power rail integration guidelines, power supply sequencing, power-on reset, and ESD guidelines.

1.8 Download