For data-center and networking applications, high-speed data enters an FPGA-based processing node in two fundamental ways: through PCIe connections to a host processor and via high-speed Ethernet connections to other data-center resources. The Speedster7t family is designed to maximize data rates over these connections with a number of PCIe Gen5 interfaces for the host-processor connection and multiple 400G Ethernet connections. Both of these I/O standards represent the fastest, most recent specifications for inter- and intra-system data communications used in data centers and many other FPGA-based applications. The Speedster7t FPGAs’ multiple, high-speed I/O ports support data rates that data centers expect to see in the near future.
Most FPGAs store data that must be accessed quickly in on-chip SRAM. The Speedster7t FPGA family is no exception, incorporating a substantial amount of on-chip SRAM. However, the amount of data that must be handled by many data-center applications almost universally overwhelms these resources, even when the FPGA in question is fabricated with 7nm FinFET process technology. Consequently, Speedster7t FPGAs are designed with multiple GDDR6 SDRAM controller ports, providing the fastest SDRAM access speeds with the lowest DRAM cost (per stored bit) and at power levels equivalent to LPDDR5 SDRAM.
Speedster7t FPGAs include multiple Ethernet subsystem ports consisting of 8 SerDes lanes and Ethernet MACs to support a combination of applications. The Ethernet MAC is very flexible and can support multiple ports and configurations up to 400G, with each SerDes lane able to achieve a line rate between 10G and 100G. This high-performance Ethernet subsystem connects to the FPGA fabric through the network on chip (NoC).
|Mode||SerDes Lanes||SerDes Rate (Per Lane)||Description|
|400G||8||50G||400G over 8 lanes|
|4||100G||400G over 4 lanes|
|200G||4||50G||200G over 4 lanes|
|2||100G||200G over 2 lanes|
|100G||4||25G or 26.5G||100G over 4 lanes (RSFEC-KR4 or RSFEC-KP4)|
|2||50G||100G over 2 lanes|
|1||100G||100G over 1 lane|
|10/25/40/50G||2||25G||50G over 2 lanes|
|1||50G||50G over 1 lane|
|4||10G||40G over 4 lanes|
Speedster7t FPGAs have multiple PCIe Gen5 interfaces with 16 lanes (×16) and 8 lanes (×8) configurations. Both PCIe controller interfaces support dual-operation, as either an endpoint or as a root complex.
|Feature||PCIe Port 1||PCIe Port 2|
|PCI Express Specification||Revision 5.0, Version 0.9||Revision 5.0, Version 0.9|
|PIPE||Version 5.1.1||Version 5.1.1|
|Maximum throughput||512 GTs (Gen 5)||256 GTs (Gen 5)|
|Supported functionality||Root-Port + End-Point||Root-Port + End-Point|
|DMA read channels||4||2|
|DMA write channels||4||2|
|Advanced error reporting (AER) support||Yes||Yes|
GDDR6 SDRAM interfaces are the best choice for next-generation system designs given their combination of high-speed and low power. Speedster7t devices contain up to eight GDDR6 interfaces to provide external high-bandwidth memory interface support. Each GDDR6 interface operates on two channels, each of which can be disabled independently.
Each controller supports a wide range of features, including bus utilization optimization, page-hit mitigation, multiport front end (MPFE), reordering and error interrupt. Users can configure the PHY ZQ calibration as master/slave mode across multiple PHY’s. Both the controller and PHY implementation are compliant with the JEDEC GDDR6 SDRAM standard JESD250.
The GDDR6 interfaces can be run up to a data rate of 16 Gbps with device densities from 8 Gb to 16 Gb, supporting up to ×16 in clamshell modes and up to ×8 in non-clamshell modes.
The GDDR6 controller connects to the FPGA fabric via an AXI interface with support for full or half-rate clocking through one of two options:
- A 256-bit AXI interface to the network on chip (NoC), delivering up to 256 Gbps of bidirectional bandwidth
- A 512-bit AXI direct-to-fabric interface, delivering up to 512 Gbps of bidirectional bandwidth
Speedster7t FPGAs include DDR4 and DDR5 memory interface support for deeper buffering requirements. The PHY and controller are implemented as hard IP and support multiple configurations such as soldered down components on PCB, UDIMM, SODIMM, RDIMM and LRDIMM modules and bit widths from x4 to x72. The interface supports up to 16 ranks and the PHY performs calibration with a microprocessor based training sequence, so the user does not need to worry about the complexity of the design. The PHY and controller support all standard features defined by the JEDEC specification and are inter-operable with memories from all major vendors. The PHY interface to the hard controller is DFI 4.0 compliant, which allows designers to replace the hard controller with their own soft controller.