Best Practices in Designing Rad-Hard and Trusted SoCs with eFPGA IP

Designing high-performance SoCs for data acceleration applications that require high levels of security and radiation tolerance is a significant challenge for the defense industry.  These applications require new high-performance SoC design techniques in order to deliver electronics that are protected from malicious threats, supply chain issues and radiation exposure. This webinar will provide a technical discussion on the challenges and best practices involved in designing high-performance eFPGA IP for integration into custom rad-hard SoCs.

You will learn:

  • Challenges and trends in developing rad-hard electronic components
  • New design techniques to develop SoCs for demanding environments
  • Pros and cons of using eFPGA IP in an SoC for accelerating your critical IP functions
  • Best practices to design rad-hard SoCs without significant circuit modification across multiple process technology nodes
     

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About the Speaker(s)
Raymond Nijssen

Raymond Nijssen – Vice President and Chief Technologist

Mr. Nijssen has over 20 years of experience in the FPGA and EDA industries in various technical and management positions. Mr. Nijssen joined Achronix as Chief Software Architect to manage the software development group, define the foundations and algorithms of the software system, and architect key aspects of the company’s FPGA architectures. In his current role, he is responsible for the productization of the company’s current products and R&D for new technologies for future products. Prior to Achronix, Mr. Nijssen was at Tabula where he was responsible for placement and timing analysis of a time-multiplexed FPGA technology. Prior to Tabula, he was one of the first engineers at Magma Design Automation, and held multiple leadership positions in charge of routing and placement, data models and customer deployment of Magma’s Blast Plan Pro hierarchy hierarchical virtual prototyping and floorplanning products for very large ASIC designs. Mr. Nijssen received his MSEE degree from Eindhoven University of Technology in The Netherlands, and after that followed its postgraduate program studying EDA for VLSI. He holds several patents related to P&R and asynchronous circuit technologies.