Accelerating to 112 Gbps PAM4 Webinar: A Real-World FPGA Implementation

Accelerating data channels to 112 Gbps PAM4 forces system designers to balance increasing throughput, scalability and density demands with concerns such as signal integrity, system architectures and time-to-market. In this webinar, technical experts from Achronix and Samtec will discuss real-world tools and solutions that optimize the signal path both inside and outside the system design. Achronix and Samtec will provide a real-world case study of implementing 112Gbps PAM4 links using the Achronix Speedster®7t FPGA and Samtec’s portfolio of high performance interconnect solutions.

You will learn:

  • What emerging applications that require 112 Gbps signals
  • How to optimize the FPGA SerDes settings for optimal signal integrity
  • Key design considerations when designing your board interconnect
     

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