Maximize Performance Using FPGAs with PCIe Gen5 Interfaces

In this webinar, you will learn how to maximize design performance using FPGAs with embedded PCIe Gen5 interfaces. You’ll see why, in addition to high-speed connectivity, you need the ability to process incoming high-bandwidth data to accelerate application performance. You'll learn how to maximize application bandwidth using FPGAs that include:

  • Embedded PCIe Gen5 x16 interfaces capable of 512 GT/s
  • High-speed network on chip capable of delivering more than 20 Tbps of bandwidth
  • High-performance GDDR6 memory interfaces
  • Optimized arithmetic units designed to support number formats needed for AI / ML workloads

We will also highlight several application use cases for PCIe Gen5 enabled FPGAs along with important FPGA design considerations to ensure maximum efficiency and bandwidth.

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About the Speaker(s)
Kent Orthner

Kent Orthner – Vice President of Engineering

Kent Orthner has over 25 years of experience working with working with all aspects of FPGA technology and high-speed silicon connectivity. At Achronix, he leads the development and implementation of our cutting-edge devices and IP solutions. Before Achronix, Kent served as the Vice President of Engineering at Arteris, where he was responsible for all hardware and software development, and where he developed and released the world’s first highly scalable and configurable cache-coherent interconnect IP. Before that, Kent spent 11 years at Altera, leading multiple cross-functional engineering teams, including IP infrastructure, system Integration tools, debug and design visibility tools, and bring-up and regression test infrastructures.   Kent’s expertise and vision drive innovation, ensuring Achronix remains at the forefront of FPGA and accelerator technology. Kent holds a Master of Engineering in Electrical Engineering from Carleton University, Canada, and a Bachelor of Applied Science in Computer Engineering from the University of Ottawa, Canada.