Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip | Achronix Semiconductor Corporation

This novel architecture has hundreds of NoC-access-points located throughout the FPGA core that can access off-chip memories and any of the high-speed PCI Express ports. This family of FPGAs also include specialized modes for the high-speed 400G Ethernet ports.

In addition, you will see how data can be streamed across the FPGA fabric using 512 Gbps NoC channels located throughout the FPGA processing array.

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	Kent Orthner – Vice President of Engineering Kent Orthner has over 25 years of experience working with working with all aspects of FPGA technology and high-speed silicon connectivity. At Achronix, he leads the development and implementation of our cutting-edge devices and IP solutions. Before Achronix, Kent served as the Vice President of Engineering at Arteris, where he was responsible for all hardware and software development, and where he developed and released the world’s first highly scalable and configurable cache-coherent interconnect IP. Before that, Kent spent 11 years at Altera, leading multiple cross-functional engineering teams, including IP infrastructure, system Integration tools, debug and design visibility tools, and bring-up and regression test infrastructures. Kent’s expertise and vision drive innovation, ensuring Achronix remains at the forefront of FPGA and accelerator technology. Kent holds a Master of Engineering in Electrical Engineering from Carleton University, Canada, and a Bachelor of Applied Science in Computer Engineering from the University of Ottawa, Canada.