Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. The Achronix FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All Achronix products are supported by best-in-class EDA software tools.
Job Description/Responsibilities
Achronix is seeking an exceptional and proactive Principal/Sr. Staff Design Engineer to become an integral part of our forward-thinking Architecture and Design team, steering the development of the next generation FPGA. In this pivotal role, successful candidates will spearhead the design of a cutting-edge portfolio, encompassing on-chip networks, subsystems, and IP, all within the latest technology nodes. As a key player, the chosen individual takes charge of and actively contributes to the architectural vision, design execution, verification, and silicon validation processes, ensuring the seamless development of high-performance FPGA subsystems. If you're passionate about pushing the boundaries of technology and eager to leave your mark on the future of FPGAs, we invite you to join our dynamic team at the forefront of innovation.
Primary Job Responsibilities
Drive the architectural vision and design at the forefront of SoC development, taking charge of defining micro-architecture and specifications. Skillfully implement RTL using SystemVerilog and/or Verilog, showcasing expertise in integrating third-party IP at the SoC level through feasibility studies. Forge a collaborative partnership with the Verification team to define comprehensive test plans, execute tests, and adeptly debug designs.
Elevate your role by leading the development of performance models, actively participating in hardware and software system design reviews. Execute flows such as Lint, CDC, Synthesis, STA, and formal verification, while closely collaborating with the Backend team on critical aspects such as floorplan, Constraints definition, and timing analysis.
Your impact extends to supporting FPGA prototyping and post-silicon system bring-up, showcasing your commitment to the full lifecycle of hardware development. Foster a culture of collaboration by actively engaging with internal and external team members, contributing to architectural decisions, and influencing the continuous improvement of development flows and methodologies.
Required Skills
- Proven experience in designing and seamlessly integrating on-chip networks with interconnect protocols like AXI, ACE, APB, etc.
- Expertise in memory controllers and PHY layers, with a focus on DDR4/5, GDDR6, and HBM2/2e considered a significant advantage
- Demonstrated expertise in Ethernet, including hands-on experience with priority-based flow control (PFC) and high-speed (100Gbps+) Ethernet, adding a distinctive edge
- Recognized as an expert RTL developer with a strong background in SystemVerilog, utilizing ASIC development techniques and design flows at modern technology nodes, encompassing synthesis and timing closure
- Strong knowledge in digital design involving multiple clock domains and clock power management
- Proficient in low-power design, tools, and methodologies, including expertise in power intent UPF specifications, considered a significant advantage
- Excellent communication and documentation skills, showcasing the ability to convey complex technical concepts with clarity and precision
Education and Experience
- A minimum of 8+ years experience in SOC/ASIC front-end design
- Bachelor or Master’s degree in Computer or Electrical Engineering
The compensation range for this position is $120,000–$190,000. Salary ranges dependent on experience and location.