SOCs Timing Closure Techniques with Embedded FPGA Fabric

Once the benefits of using an embedded FPGA fabric are understood, the next question is about how timing closure is handled between the ASIC and the eFPGA blocks. First let’s look briefly at the advantages. By moving the eFPGA on to the SOC die, tons of I/O logic and the need for any package and board interconnect will vanish. Package and board routing create messy signal integrity and timing issues that require SerDes and bus protocols to tame. The added benefits also include reduced power – less logic to drive – and much lower latency. Instead of using a pair of SerDes, now the ASIC and eFPGA talk over direct wired signal nets.