eFPGAs are embeddable IP that include look-up tables, memories, and DSP building blocks, allowing designers to add a programmable logic fabric to their SoC. The Speedcore IP can be configured to any size as dictated by the end application. The SoC supplier defines the number of LUTs, memory resources, and DSP64 blocks for their Speedcore instance. A short time later, Achronix delivers the IP as a GDS plus supporting libraries, models and documentation. Once this custom Speedcore block is embedded in the SoC, the end user can use the Achronix CAD Environment (ACE) design tools which are traditional FPGA design tools and workflows to target the embedded FPGA. For more details on the roles and responsibilities in an eFPGA engagement, see the blog post Who’s Who in the Zoo.
SoC timing closure is generally a complex task — a task that is further complicated by an eFPGA in the SoC. In this case there are no traditional I/O buffers at the interface of the fabric to the host ASIC that create a clear boundary from a timing perspective, nor does the end user control the logic connecting to the eFPGA instance as they would with a standalone FPGA mounted to a PCB. The SoC supplier must deliver the design files to the end user describing the timing at the interface to the Speedcore instance plus the defined pin out, in effect turning the rest of the SoC into a complex I/O ring for the Speedcore instance.