Intel announced this week that they have begun shipping the first of their new Agilex FPGAs to early-access customers. This moves us into what we historically think of as the “head-to-head” phase of the competition between the two biggest FPGA suppliers. Xilinx shipped their first “Versal ACAP” FPGAs back in June, so, after a very long and contentious “who is going to ship first?” battle, it turns out the two rival companies began shipping their comparable FPGA lines within about two months of each other. This means that, unlike other recent races to be first on a process node, neither company had any significant time to scoop up design wins with a new, superior technology uncontested by a rival.
This time around, though, the competitive field is one larger, with interloper Achronix claiming they are set to ship the first samples of their new Speedster 7t FPGAs by the end of this year. For development teams, this means that, by the end of the year, there will be three well-differentiated high-end FPGA offerings to choose from – all on comparable process technology, and all with intriguing unique features and capabilities.
This will be the first of a multi-part series comparing the new high-end FPGA families from these three vendors. We’ll look at the underlying process technology, the FPGA logic (LUT) fabric itself, the hardened resources for accelerating processing and networking, memory architectures, chip/package/customization architecture, IO resources, design tool strategy, unique and novel features and capabilities of each offering, and marketing strategy. Buckle up, it’ll be an exciting ride. Uh, if you’re the type who gets a thrill out of enormous numbers of FLOPS, crazy bandwidths, and some of the most interesting and capable semiconductor devices ever designed.
A note – both Intel and Achronix weighed in and provided info for this article. Xilinx did not respond to our request for information.
This time, the prize for high-end FPGA supremacy has morphed somewhat. In the past, the largest market for high-end FPGAs was in networking, and the market share line shifted ever-so-gradually – primarily based on who could capture the richest set of design wins with a new-generation family from the customers deploying the latest round of wired and wireless networking hardware. The timing of the 5g rollout has changed that dynamic, however. 5g began ramping to scale prior to the arrival of the current wave of FPGA technology, so the backbone of the first round of 5g is built on previous-generation programmable logic. These devices will flow into an already robust 5g ecosystem, so we don’t have alignment between the clean-slate revolution of 5g and the dawn of a new generation of FPGAs. These FPGAs were designed with the mechanics of 5g already pretty well understood. Do not underestimate the importance of FPGAs to 5g, or of 5g to the FPGA market, however. When you use your cell phone today, there’s about a 99% chance that your call is going through some FPGAs. With 5g, the impact of FPGAs will be even greater.
That fact plays an interesting game with the rapid expansion of the emerging market for data center acceleration – primarily for AI workloads. Estimates are that the market for AI acceleration will skyrocket over the next few years, and these devices – with their impressive price tags and non-trivial power budgets – are set to compete mostly for the data center portion of that market, although all three vendors claim to be offering solutions that help all the way to the edge/endpoint. Each of these vendors makes it very clear that capturing those AI acceleration sockets is a priority, and they’ve all architected their new chips around that idea. The combination of these factors has set the stage for these three companies to be competing ferociously on both the 5g and the AI acceleration fronts – meaning that these devices need to have robust AI acceleration features, stellar networking performance, a robust set of development tools for deploying these ultra-complex chips, and a cunning marketing strategy.
Let’s look at all those factors, shall we?
Starting with the underlying process technology, Xilinx and Achronix FPGA families are fabricated on TSMC 7nm, and Intel Agilex is fabricated on the similar-capability Intel 10nm process. Don’t be confused by the 7/10 nomenclature difference. We long ago reached the point where semiconductor marketing groups name the nodes based on what sounds good to the market, rather than deriving them from any discernible feature of the transistors themselves. By our estimation, TSMC’s 7nm and Intel’s 10nm are roughly equivalent processes, and vendors using both processes basically agree. This means that Intel’s long-held lead in process technology seems to have whithered to a vapor, but, as we approach the dusk of Moore’s Law, it is inevitable that the competitive field on silicon process will level itself.
All three vendors get a modest boost from jumping to the latest semiconductor process node. This jump is not likely to be up to historical Moore’s Law standards, however, as the incremental benefits from each new process update have been steadily declining over the past several nodes. Everyone got a one-time temporary boost when FinFET technology came along, and now we will probably see a continuation of the trend of diminishing marginal return as we move forward toward the coming economic end of Moore’s Law.