High-end vehicles with advanced driver-assistance systems (ADAS), including advanced safety features such as emergency braking, lane-changing assist, adaptive cruise control, and automate braking, are now entering the market. These high-end vehicles are chocked full of features beyond ADAS: advanced infotainment, complex cabin environment controls, infrared vision, etc.). Today, the ADAS processor market is growing by more than 25% per year, driven by the migration of ADAS features from luxury vehicles to mid-range and entry-level vehicles. These features will be close to universal by the middle of the next decade.
Meanwhile, level-3 autonomous vehicles are arriving in 2018 in luxury platforms such as the BMW i7. These vehicles are capable of piloting in traffic with only minimal human assistance and pave the way for levels 4 and 5 vehicles (ones that are fully autonomous). As a result, the current base of up to 100 CPUs in luxury piloted vehicles could swell to several hundred CPUs in autonomous vehicles.
The favored automotive intelligence model of just a few years ago, promoted by Nvidia, Mobileye, and other CPU-centric suppliers, assumed a centralized automotive network in which multi-core RISC CPUs with enhanced DSP capabilities managing a suite of specialized subnetworks. Today, attention is rapidly shifting to decentralized automotive intelligence, in which complex cameras with associated vision systems, sensor subnetworks, ADAS, and drive-train/power train subnetworks, all collaborate to implement needed functions. Sensor hubs will require look-aside image processing for warp and stitch effects. Ethernet networks will require IP for packet filtering/monitoring, as well as special bridges to legacy CAN and FlexRay networks. The use of CPUs and GPUs in first-generation automotive architectures will migrate to highly specialized compute nodes requiring programmable hardware acceleration.