The Speedster®22i HD core is arranged with columns of reconfigurable logic blocks (RLB) interspersed with columns of block RAMs (BRAM), block multiply accumulators (BMAC) and logic RAMs (LRAM). A fabric of horizontal and vertical interconnect connects the FPGA core resources together.



Each reconfigurable logic block (RLB) has ten LUTs that are divided into five logic clusters, each containing two LUTs and two registers.Each RLB has three light logic cluster (LLC) and two heavy logic cluster (HLC). The HLC is a super-set of the LLC and includes an advanced carry that is cascaded through multiple RLBs.



The block RAM (BRAM) contained within the Speedster22i is an 80 Kbit, true dual-port (asynchronous) memory capable of operation at up to 750 MHz and can be configured as any of the following:

2k × 40, 2k × 36, 2k × 32, 4k × 20, 4k × 18, 4k × 16, 8k × 10, 8k × 9, 16k × 5, 16k × 4, 32k × 2 or 64k × 1

Additionally, each BRAM has a FIFO controller built into it and is capable of operating with two independent ports with asynchronous or synchronous access.



For smaller memory requirements, each LRAM implements a 640-bit memory block with one write port and one read port. The LRAM can be configured as either:

  • 64 × 10 simple dual-port RAM
  • 64 × 10 single-port RAM



The multiply-accumulator (BMACC56) block implements a signed 28 × 28 multiplier followed by an optional accumulator block and operates at up to 750 MHz. The multiplier produces a 56-bit result which is fed into (or bypasses) the 56-bit accumulator.