| Video | Title | Published Date |
|---|---|---|
What Are The Challenges Facing SmartNIC Designers?In this discussion with Electronic Design's Bill Wong, Achronix Director of SmartNIC Product Planning, Scott Schweitzer addresses design issues for SmartNICs ranging from BMC complexes to the need for programmable logic. |
||
The Most Exciting Time in the FPGA IndustrySteve Mensor, VP of Sales and Marketing, discusses why this is the most exciting time in the FPGA industry over the past 30 years. He provides an Achronix business update on Speedster7t FPGAs and Speedcore eFPGA IP and the growing opportunities across a wide range of high-performance applications. |
||
The Basics of eFPGA Acceleration |
||
The Achronix Validation Platform DemonstrationAchronix Speedcore eFPGA IP opens new opportunities for companies looking to integrate embedded FPGA technology into their ASIC or SOC. Speedcore IP is a high-performance, customizable programmable fabric, allowing customers to define the amount of logic, memory, DSP plus their own custom blocks to fit their application requirements. This video demonstrates a validation platform for this game-changing technology. |
||
Steve Mensor at ArmTechCon 2018Steve Mensor presents at ArmTechCon 2018. Topic: “Accelerate your Arm-based SoC with Speedcore eFPGA IP” |
||
Robert Blake at the CASPA 2018 Annual ConferenceRobert Blake presenting at the CASPA 2018 Annual Conference. Topic: "Addressing AI/ML Hardware Challenges." |
||
Redefining Hardware Architectures with Chiplet TechnologyRosenblatt's Senior Semiconductor Analyst, Kevin Cassidy, hosts a timely and informative webinar — featuring Achronix CEO, Robert Blake, and Laura Mirkarimi, SVP of Engineering from Adeia — outlining the critical role chiplets will play in piecing together the chips of the future with more performance, less power and quicker time to market. |
||
Nasdaq Trade Talks: Enabling Technology for Data AccelerationAchronix CEO Robert Blake joins Jill Malandrino on Nasdaq #TradeTalks to discuss enabling technology for data acceleration. |
||
Modular SmartNIC Design Using FPGAsDiscover the power of SmartNICs with Achronix! Scott Schweitzer, Director of Product Marketing, introduces our modular FPGA approach to high-speed data processing. With up to five relocatable and dynamically placeable modules, you can customize your network packet management or dive into advanced network flows. |
||
Learning to Share – Embedded FPGA Timing ClosureAchronix Systems Architect, Kent Orthner, speaking at DAC 2018 in San Francisco. |
||
Increase Performance, Reduce Die Size with Speedcore eFPGA Custom Blocks FlowAchronix Vice President of Marketing, Steve Mensor, speaking at DAC 2018 in San Francisco. |
||
How to Time an eFPGA, and What Can Go WrongNamit Varma, senior director of Achronix’s India Technology Center, explains how to time an eFPGA, what can go wrong, what are the different clocking scenarios, and what impact variation has on the process. |
||
How to Program an eFPGAKent Orthner, system architect at Achronix, talks with Semiconductor Engineering about how to program an embedded FPGA and what's different for ASIC engineers. |
||
From 40-500 MHz eFPGA to FPGA Chiplet SolutionDesign and Reuse interview with Steve Mensor, VP of Marketing, at DAC 2018, San Francisco, CA; June 24-28th. |
||
Embedded FPGA: Enabling 5G InfrastructureFormer Achronix Sr. Director of Strategy and Planning discusses the role of eFPGAs in 5G infrastructure at the IP SoC Days 2018, Santa Clara, USA.on April 5th, 2018 |
||
Embedded Computing Design Interview with Steve Mensor at Arm TechCon 2018Brandon Lewis, Editor-in-Chief of Embedded Computing Design sits down with Achronix VP of Marketing, Steve Mensor, to discuss how to deal the growing volume of data that will require to be processed to drive the next wave of AI applications. |
