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Achronix Demonstrates Silicon Validation Device with 112 Gbps SerDes

Achronix has completed testing and is now demonstrating the 112 Gbps SerDes that will be used in its next- generation FPGAs devices. Fabricated on TSMC’s 7nm FinFET process technology, these 112 Gbps SerDes blocks provide true multi-standard support for a wide range of digital serial communications standards with data rates ranging from 1 Gbps to …

Released: 3/27/2019 - Tags: [SerDes] [Alphawave]

Achronix Speedcore Gen4 eFPGA IP for AI/ML and Networking Hardware Acceleration

Steve Mensor, VP of Marketing at Achronix previews the coming announcement of the next-generation Speedcore architecture.

Released: 10/26/2018 - Tags: [speedcore] [Arm TechCon]

Steve Mensor at ArmTechCon 2018

Steve Mensor presents at ArmTechCon 2018. Topic: “Accelerate your Arm-based SoC with Speedcore eFPGA IP”

Released: 10/24/2018 - Tags: [speedcore] [eFPGA] [Arm TechCon]

Robert Blake at the CASPA 2018 Annual Conference

Robert Blake presenting at the CASPA 2018 Annual Conference. Topic: “Addressing AI/ML Hardware Challenges.”

Released: 10/24/2018 - Tags: [speedcore] [eFPGA] [CASPA]

eFPGA vs. FPGA Design Methodologies

Namit Varma, senior director of Achronix’s India Technology Center, discusses the differences between discrete and embedded FPGAs.

Released: 10/05/2018 - Tags: [tech talk] [speedcore] [Semiconductor Engineering]

How to Time an eFPGA, and What Can Go Wrong

Namit Varma, senior director of Achronix’s India Technology Center, explains how to time an eFPGA, what can go wrong, what are the different clocking scenarios, and what impact variation has on the process.

Released: 8/02/2018 - Tags: [tech talk] [speedcore]

Increase Performance, Reduce die size with Speedcore eFPGA Custom Blocks Flow

Achronix Vice President of Marketing, Steve Mensor, speaking at DAC 2018 in San Francisco.

Released: 7/27/2018 - Tags: [speedcore] [DAC]

Learning to Share – Embedded FPGA Timing Closure

Achronix Systems Architect, Kent Orthner, speaking at DAC 2018 in San Francisco.

Released: 7/27/2018 - Tags: [speedcore] [DAC]

From 40-500 MHz eFPGA to FPGA Chiplet Solution

Design and Reuse interview with Steve Mensor, VP of Marketing, at DAC 2018, San Francisco, CA; June 24-28th.

Released: 6/28/2018 - Tags: [interview] [speedchip] [FPGA chiplets] [DAC]

Embedded FPGA: Enabling 5G Infrastructure

Mike Fitton, Senior Director, Strategic Planning, Achronix discusses the role of eFPGAs in 5G infrastructure at the IP SoC Days 2018, Santa Clara, USA.on April 5th, 2018

Released: 4/05/2018 - Tags: [interview] [speedcore] [5G]

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