Advanced FPGAs that provide the right blend of flexibility and capability are ideal for test and measurement applications. In particular, Achronix’s Speedster22i FPGAs are especially well-suited to such application, which have challenging memory capacity and memory bandwidth requirements.

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Speedster22i devices offer I/O with unique test-friendly capabilities. The user I/O provide the ability to:

  • Add fine-gained delay on a per I/O basis
  • Perform logical operations on individual signal edges

For example, these features enable fine-grained manipulation of pulse widths on outputs signals. Also, the SerDes transceivers can operate in “lock to reference” mode, allowing data transfer to and from a device under test (DUT), without requiring data encoding (data encoding may be incompatible with DUT operation).

The diagram illustrates a Speedster22i HD1000 device in a production semiconductor tester. Memory bandwidth is provided by the embedded DDR3 controllers. The embedded DDR3 controllers are fully functional and do not use any of the FPGA programmable resources. The DDR3 memory bandwidth can be used for the following:

  • Stimulus vector for data to be streamed to the system under test
  • Captured responses of data retrieved from the SUT and stored for analysis

In these applications, traffic is largely unidirectional and transferred in large contiguous blocks, maximizing the strengths of DDR3 interface. Also these DDR3 controllers are fully embedded as hardened IP blocks in the Speedster22i devices. Thus the FPGA can perform more tasks, potentially absorbing the functions of other devices-lowering devices count and complexity.

Speedster22i devices excel in memory capacity and bandwidth with independent, built-in DDR3 controllers that provide over 920 Gbps of memory bandwidth. They also provide up to 144 Mb of embedded RAM in the form of block and distributed RAM.

Energy efficiency is another key driver of today’s advanced applications and Speedster22i devices, built on Intel’s advanced 22nm process, consume less power than competitive high-end FPGAs.

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Requirements

  • Substantial data path bandwidth for high traffic volume
  • Substantial external memory capacity for traffic buffering
  • Substantial external memory bandwidth
  • Substantial login capacity to implement complex queuing algorithms
  • Substantial internal memory for queuing pointers, policy tables and scratchpad RAM

Provided by Speedster22i FPGAs:

  • Up to 200 Gigabit Ethernet and 200 Gigabit Interlaken
  • Up to six independent DDR3 ×72 interfaces at 1600 Mbps
  • Up to 691 Gbps of raw memory bandwidth
  • Up to 1 million effective LUTs
  • Up to 86 Mb of internal SRAM

Speedster22i devices contain hard IP blocks for the interfaces described above. These fully-hardened IP blocks provide the following benefits:

  • Consume no programmable resources (LUTs, memory and routing)
  • Require no timing-closure (timing guaranteed by design)
  • Consume less power
  • Contribute less latency
  • Require no license fees
  • Fully bypassable, so that I/O and SerDes lanes can be freely used for other purposes

The hard-wired nature of these blocks leaves more fabric logic available, which can be used for additional functions, including:

  • Test sequence control
  • Data streaming to and from the DUT
  • Error-rate analysis
  • Statistics gathering for billing and network management
  • Preparing results for the external analysis/display subsystem

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