Documentation

Download the latest versions of Achronix application notes, datasheets, product briefs, user guides and white papers.

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Title Description Version Released Date Document File
Software-Defined Hardware Provides the Key to High-Performance Data Acceleration (WP019)

Across a wide range of industries, data acceleration is the key to building efficient, smart systems. A number of accelerator technologies have appeared to fill the gap that are based on custom silicon, graphics processors or dynamically reconfigurable hardware, but the key to their success is their ability to integrate into an environment where high throughput, low latency and ease of development are paramount requirements. A board-level platform developed jointly by Achronix and BittWare has been optimized for these applications, providing developers with a rapid path to deployment for high-throughput data acceleration.

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The Achronix Integrated 2D NoC Enables High-Bandwidth Designs (WP028)

Devices aimed at addressing modern algorithm acceleration workloads must be able to efficiently move high-bandwidth data streams between high-speed interfaces and throughout the device. Achronix Speedster®7t FPGAs can process these high-bandwidth data streams via an integrated new and highly innovative two-dimensional network on chip (2D NoC). This white paper discusses two methods of implementing a 2D NoC and presents an example design to show how the Achronix 2D NoC improves performance, reduces area, and reduces design time when compared to a soft 2D NoC implementation.

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The AI Evolution Calls for Adaptable Inferencing Platforms (WP023)

Deep learning's demand for computing power is growing at an incredible rate, accelerating recently from doubling every year to doubling every three months. Increasing the capacity of deep neural network (DNN) models has shown improvements across a wide range of areas ranging from natural language processing to image processing. This growth calls for the adoption of customized architectures that squeeze the greatest amount of performance out of each transistor available.

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The Ideal Solution for AI Applications — Speedcore eFPGAs (WP011)

AI requires a careful balance of datapath performance, memory latency, and throughput that requires an approach based on pulling as much of the functionality as possible into an ASIC or SoC. But that single-chip device needs plasticity to be able to handle the changes in structure that are inevitable in machine-learning projects. Adding eFPGA technology provides the mixture of flexibility and support for custom logic that the market requires. Achronix provides not only the building blocks required for an AI-ready eFPGA solution, but also delivers a framework that supports design through to debug and test of the final application. Only Achronix Speedcore IP has the right mix of features for advanced AI that will support a new generation of real-time, self-learning systems.

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Using FPGAs to Accelerate Data Centers (WP005)

With the technology industry at a crossroads — the effective repeal of Moore's Law  — data centers have become the sweet spot of the technology sector, showing healthy revenue growth and attracting new system solutions in both hardware and software. Unlike the ethereal promise of upcoming wonders from AI, robotics and the IoT, data center growth and innovation is happening in the here and now, with an even brighter future ahead the moment other nascent markets emerge from their chrysalis with killer apps of their own.

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Title Description Version Released Date Document File
Speedster7t DDR User Guide (UG096)

The Achronix Speedster7t FPGA family provides DDR subsystems that enable the user to fully utilize the low latency and high-bandwidth efficiency of these interfaces for critical applications such as high-performance compute and machine learning systems. The DDR subsystem supports memory devices and features compliant with JEDEC Standard JESD79-4B.

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Speedster7t Ethernet User Guide (UG097)

Speedster7t devices include high-speed Ethernet interfaces, which can support a wide variety of Ethernet packet protocols and speeds of up to 400 Gbps per channel. These Ethernet interfaces are paired with latest generation SerDes which individually support 100 Gbps data rates. With eight of these SerDes per Ethernet interface, each interface can support 2× 400 Gbps Ethernet IP channels.

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Speedster7t GDDR6 User Guide (UG091)

The Speedster7t FPGA family provides multiple GDDR6 subsystems enabling full utilization of the high-bandwidth efficiency of these interfaces for critical applications. This guide provides the details for implementing the GDDR6 IP in custom designs.

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Speedster7t GPIO User Guide (UG112)

This document describes the Speedster7t FPGA GPIO pins, their various features, how to configure them, any design considerations to be taken into account, and the tools required to implement them.

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Speedster7t Machine Learning Processor User Guide (UG088)

The machine learning processor block (MLP) is an array of up to 32 multipliers, followed by an adder tree, an accumulator, and a rounding/saturation/normalize block.The MLP also includes two memory blocks, a BRAM72k and LRAM2k, that can be used individually or in conjunction with the array of multipliers. The number of multipliers available varies with the bit width of each operand and the total width of input data. When the MLP is used in conjunction with a BRAM72k, the amount of data inputs to the MLP block increases along with the number of multipliers available. 

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